SCLS508D June 2003 – September 2025 SN74AHCT125-Q1
PRODUCTION DATA
The SN74AHCT125-Q1 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To establish the high-impedance state during power up or power down, tie down the OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.