7.6.1 Scratch_Register (Offset = 0h) [Reset = 00h]

Scratch_Register is shown in Table 7-5.

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The scratch register is a test register to read/write code from/to a blank register and resolve any coding issues

7.6.2 Device_ID_Register (Offset = 10h) [Reset = 01h]

Device_ID_Register is shown in Table 7-6.

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The device identification register that has the device ID.

7.6.3 Input_Port_Register_y (Offset = 20h + formula) [Reset = XXh]

Input_Port_Register_y is shown in Table 7-7.

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The input port register reflects the incoming logic level of the pins for the port, regardless of whether the configuration register defines the pin as an input or output. The input port registers are read only. Writes to these registers have no effect. The externally applied logic level determines the default value.

Offset = 20h + (y * 1h); where y = 0h to 2h

7.6.4 Output_Port_Register_y (Offset = 30h + formula) [Reset = 00h]

Output_Port_Register_y is shown in Table 7-8.

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The output port register reflect the outgoing logic levels of the pins Py.0 to Py.7, when defined as outputs by the configuration register. Bit values in the register have no effect on pins defined as inputs. Reads from the register reflect the value that is in the register and not the actual pin value.

Offset = 30h + (y * 1h); where y = 0h to 2h

7.6.5 Direction_Configuration_Register_y (Offset = 40h + formula) [Reset = 00h]

Direction_Configuration_Register_y is shown in Table 7-9.

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The direction configuration registers configure the direction of the I/O pins. If a bit in the register is set to 0, the corresponding port pin is enabled as a high-impedance input. If a bit in the register is set to 1, the corresponding port pin is enabled as an output.

Offset = 40h + (y * 1h); where y = 0h to 2h

7.6.6 Polarity_Inversion_Register_y (Offset = 50h + formula) [Reset = 00h]

Polarity_Inversion_Register_y is shown in Table 7-10.

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The polarity inversion register allows polarity inversion of pins Py.0 to Py7, defined as inputs by the configuration register. If a bit in this register is set, the corresponding pin's polarity is inverted. If a bit in the register is cleared, the corresponding pin's polarity is retained.

Offset = 50h + (y * 1h); where y = 0h to 2h

7.6.7 Push_Pull/Open_Drain_Selection_Register_y (Offset = 60h + formula) [Reset = 00h]

Push_Pull/Open_Drain_Selection_Register_y is shown in Table 7-11.

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The push pull / open drain selection register is used to select the pin as push-pull or open-drain. When the bit is set, the corresponding pin is configured as open-drain (Q1 is disabled and Q2 is active). When the bit is cleared, the corresponding pin is configured as push-pull (Q1 and Q2 are active).

Offset = 60h + (y * 1h); where y = 0h to 2h

7.6.8 Pull-up/Pull-down_Enable_Register_y (Offset = 80h + formula) [Reset = 00h]

Pull-up/Pull-down_Enable_Register_y is shown in Table 7-12.

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The pull-up/pull-down enable register allows the user to enable or disable pull-up/pull-down resistors on the GPIO pins. Setting the bit enables the selection of pull-up/pull-down resistors on the pins. Clearing the bit disconnects the pull-up/pull-down resistors from the pins. The resistors are disabled when the corresponding pins are configured as outputs.

Offset = 80h + (y * 1h); where y = 0h to 2h

7.6.9 Pull-up/Pull-down_Selection_Register_y (Offset = 90h + formula) [Reset = 00h]

Pull-up/Pull-down_Selection_Register_y is shown in Table 7-13.

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The pull-up/pull-down selection register allows the user to configure each GPIO pin to have a pull-up or pull-down resistors. Setting the bit enables the pull-up resistors on the pins. Clearing the bit enables the pull-down resistors on the pins. If the pull-up/pull-down feature is disabled, then writing to the register will have no effect.

Offset = 90h + (y * 1h); where y = 0h to 2h

7.6.10 Bus_Holder_Register_y (Offset = A0h + formula) [Reset = 00h]

Bus_Holder_Register_y is shown in Table 7-14.

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The bus holder register enables or disables the bus-hold or bus-keeper function of the GPIO pins. The feature is available only when the pin is configured as an input pin. When the register bit is set, the corresponding input pin state holds the line at its last known logical state when the device driving the pin floats its output.

Offset = A0h + (y * 1h); where y = 0h to 2h

7.6.11 Smart_Interrupt_Register (Offset = B0h) [Reset = 00h]

Smart_Interrupt_Register is shown in Table 7-15.

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The register is used to enable or disable the smart interrupt function. When the bit is set to 0 (smart interrupt enabled), a state change in any input pin generates an interrupt and if the input goes back to its initial state, the interrupt is cleard.
When the bit is set to 1 (smart interrupt disabled), a state change in any input pin generates an interrupt and if the input goes back to its initial state, the interrupt is not cleared. A read of the interrupt status flag register will clear the interrupt.
This feature is enabled at the port level only.

7.6.12 Interrupt_Mask_Register_y (Offset = C0h + formula) [Reset = FFh]

Interrupt_Mask_Register_y is shown in Table 7-16.

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The interrupt mask register enables or disable interrupt generation from pins. If the mask register bit is set, and the input state of a pin changes, then interrupt is not asserted. If the mask register bit is cleared, and the input state of a pin changes, then interrupt is asserted.

Offset = C0h + (y * 1h); where y = 0h to 2h

7.6.13 Interrupt_Glitch_Filter_Enable_Register_y (Offset = D0h + formula) [Reset = 00h]

Interrupt_Glitch_Filter_Enable_Register_y is shown in Table 7-17.

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The interrupt glitch filter register enables or disable the glitch filter on the I/O. If the bit is set to 1, the glitch filter for the corresponding pin is enabled. If the bit is set to 0, the glitch filter for the corresponding pin is disabled.

Offset = D0h + (y * 1h); where y = 0h to 2h

7.6.14 Interrupt_Flag_Status_Register_y (Offset = E0h + formula) [Reset = 00h]

Interrupt_Flag_Status_Register_y is shown in Table 7-18.

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The interrupt status register is read only register bits used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of the an interrupt. When the corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return a logic 0.

Offset = E0h + (y * 1h); where y = 0h to 2h

7.6.15 Interrupt_Port_Status_Register (Offset = F0h) [Reset = 00h]

Interrupt_Port_Status_Register is shown in Table 7-19.

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The register is used to identify the IO port for the interrupt source. If the value of the bit is 1, it indicates that the source of the interrupt is from the corresponding IO port. If the value is 0, it indicates that none of the input pins in the IO port generated an interrupt.

7.6.16 Fail-Safe_Enable_Register-1 (Offset = 120h) [Reset = 00h]

Fail-Safe_Enable_Register-1 is shown in Table 7-20.

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This register reconfigures the reset pin as a fail-safe pin. The register is cleared on POR or fault condition as mentioned in the fault status register.
There are two fail-safe registers in the device that have to be written to program the I/O configuration with built-in redundancy. If the value in the two registers mismatch, it will generate an interrupt with fault status set accordingly.

7.6.17 Fail-Safe_Enable_Register-2 (Offset = 130h) [Reset = 00h]

Fail-Safe_Enable_Register-2 is shown in Table 7-21.

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This register reconfigures the reset pin as a fail-safe pin. The register is cleared on POR or fault condition as mentioned in the fault status register.
There are two fail-safe registers in the device that have to be written to program the I/O configuration with built-in redundancy. If the value in the two registers mismatch, it will generate an interrupt with fault status set accordingly.

7.6.18 Fail-Safe_Direction_Configuration_Register-1_y (Offset = 140h + formula) [Reset = 00h]

Fail-Safe_Direction_Configuration_Register-1_y is shown in Table 7-22.

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The fail-safe direction configuration register-1 configure the direction of the I/O pins when the device enters a fail-safe state. If a bit in these register is set to 0, the corresponding IO pin is enabled as a high-impedance input during fail-safe mode. If a bit is set to 1, the corresponding IO pin is enabled as an output during fail-safe mode.
There are two registers per port, that have to be written to program the I/O configuration to ensure redundancy. If the registers mismatch, it will generate an interrupt with fault status set accordingly.

Offset = 140h + (y * 1h); where y = 0h to 2h

7.6.19 Fail-Safe_Direction_Configuration_Register-2_y (Offset = 150h + formula) [Reset = 00h]

Fail-Safe_Direction_Configuration_Register-2_y is shown in Table 7-23.

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The fail-safe direction configuration register-2 configure the direction of the I/O pins when the device enters a fail-safe state. If a bit in these register is set to 0, the corresponding IO pin is enabled as a high-impedance input during fail-safe mode. If a bit is set to 1, the corresponding IO pin is enabled as an output during fail-safe mode.
There are two registers per port, that have to be written to program the I/O configuration to ensure redundancy. If the registers mismatch, it will generate an interrupt with fault status set accordingly.

Offset = 150h + (y * 1h); where y = 0h to 2h

7.6.20 Fail-Safe_Output_Register-1_y (Offset = 160h + formula) [Reset = 00h]

Fail-Safe_Output_Register-1_y is shown in Table 7-24.

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The fail-safe output register-1 configure the output level of the pins defined as output by the fail-safe configuration register. Bit values in the register have no effect on pins defined as input.
There are two registers per port, that have to be written to with the same output value to ensure redundancy. If the registers mismatch, it will generate an interrupt with fault status set accordingly.

Offset = 160h + (y * 1h); where y = 0h to 2h

7.6.21 Fail-Safe_Output_Register-2_y (Offset = 170h + formula) [Reset = 00h]

Fail-Safe_Output_Register-2_y is shown in Table 7-25.

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The fail-safe output register-2 configure the output level of the pins defined as output by the fail-safe configuration register. Bit values in the register have no effect on pins defined as input.
There are two registers per port, that have to be written to with the same output value to ensure redundancy. If the registers mismatch, it will generate an interrupt with fault status set accordingly.

Offset = 170h + (y * 1h); where y = 0h to 2h

7.6.22 Fail-Safe_Redundancy_Check_Register (Offset = 180h) [Reset = 00h]

Fail-Safe_Redundancy_Check_Register is shown in Table 7-26.

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The fail-safe redundancy check register is used to enable the check on the fail-safe redundant registers (fail-safe enable register, fail-safe direction configuration register and fail-safe output register).

7.6.23 Fault_Status_Register (Offset = 190h) [Reset = 01h]

Fault_Status_Register is shown in Table 7-27.

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The fault status register are set during fault conditions. Bit-0 is set to 1 for POR recovery. Bit-1 is set when the redundancy register has a mismatch. Bit-2 is set when the device is in fail safe mode. These flags are not cleared even if the fault condition goes away. They can only be cleared by performing a read of the fault status register.

7.6.24 Software_Reset_Register (Offset = 1A0h) [Reset = 00h]

Software_Reset_Register is shown in Table 7-28.

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The register is used to trigger a software reset of the device. The register is auto-cleared when the reset state is entered.