3 Layout Design Guide

One step in improving solution size is pulling external components as close to the integrated circuit as is manufacturable. Current-carrying traces need to be prioritized for least resistance, while digital and control signals can be broken out using smaller traces and deeper layers. Most of the current-carrying pins are directly accessible on the top layer so routing these signals is fairly straightforward. By leaving some pins unused, other signals can be routed on a lower layer that are otherwise blocked by a routing via. For instance, the D2 pin (CE) typically requires a via to be routed out since the pin is blocked in all directions from being routed out in the top layer. Without this via, the GPIO3 and GPIO4 signals can be routed on a lower layer in the space below the D2 pin.

Typically, the VINLS capacitors require pins B2 and C2 to be routed out, which require the LDO capacitors to be pulled further away from the device and increase the solution size. Shorting both to VPU and SYS allows the pins to be routed out on the surface and shorted to SYS. Resistance between the VINLS pins and SYS pin need to be minimized. To minimize noise, TI recommends that the second layer be kept an unbroken GND plane. Figure 3-1 illustrates the signal fan out on this design. Figure 3-2 clarifies the placement of the various passive components. If the ADC pin function is not used, then the SYS rail can be routed diagonally from D5 through C4, to C3, C2, and B1 all on the top layer.

Access to the internal pins, of B3, C3, D3, and E3 reduce the need for blind vias as present in the BQ25190EVM. This also reduces the cost PCB manufacturing.

Figure 3-1 BQ25190 Layout with Signal Names

Figure 3-2 BQ25190 Layout with Component Labels