2 Schematic Design Guide

For the BQ25190, optimizing for space means minimizing component counts, identifying unused pins, alternate connection paths, and selecting the smallest valid components.

The device offers four GPIOs, each with various functions accessible via register programmability. Pins GPIO3 and GPIO4, by default, are used in determining default buck output voltage. The voltage is dependent on GPIO3 and GPIO4 being pulled high, or low, to select one of four default voltages:

For configurability these signals are typically routed out to a pull-up or pull-down resistors. By selecting the best default voltage and directly tying these pins to either GND or SYS, the need for pull-up or pull-down resistors is eliminated.

Component selection can be optimized for space at the cost of some application performance limitations. The table below demonstrates a comparison of component selection between the EVM and the small solution size, as well as a size comparison:

These component selections do have impact on performance, but the total solution size is improved. C_IN has a reduced capacitance and a reduced rated voltage. This shrinks the operational input voltage range for this application. The changes in inductors (I_BB and I_BK) have an impact on efficiency due to the changes in DCR. The VINLS capacitors are not needed for this scenario due to the capacitance already on the SYS line and low resistance between VINLS pins and SYS nodes, though this can have an impact on very-fast transient load performance.

Unused pins left as No Connect can reduce the routing requirements of the board and make routing out the signals that are needed easily. Less signals with routing out of the IC means that passive components to be pulled in closer. Table 2-1 shows are some signals that can be left open but still allow critical charging and power rail operations: