SDAA108 October   2025 LM5171 , LM5171-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Circuit Differences Between Channels
  6. 3Design of External Error Amplifier Circuit
  7. 4Design of Additional OVP Circuit
  8. 5Common Settings
  9. 6Constant Current Operation with ISETx Clamping
  10. 7Summary
  11. 8References

3 Design of External Error Amplifier Circuit

When operating CH2 in voltage mode, external error amplifiers are required. Figure 3-1 shows the block diagram of the two channels. External error amplifiers OPA1 and OPA2 are used for CH2.

Two Channels of LM5171 with External Operational Amplifiers for CH2 Figure 3-1 Two Channels of LM5171 with External Operational Amplifiers for CH2

Consider the features below when designing the external error amplifier circuit,

  • The handover of the two loops when two outer loops are used.
  • The soft start of the reference voltages (VSETH and VSETL).

An example is shown in Figure 3-2.

Two common cathode diodes are used, so that the error amplifier with higher output voltage takes over the loop.

Supply the error amplifiers and logic gates with LM5171 VDD pin. The VDD pin is the output of the internal 5V linear regulator. Do not draw more than 10mA from VDD.

The VREF pin is a 1% tolerance 3.5V voltage reference with a load capacity of 2mA. Use resistor dividers from VREF pin to set the reference voltages (VSETH and VSETL).

Pay attention to the operational amplifier common mode input voltage range when selecting VSETH and VSETL voltage level. With the supply of VDD, widely used operational amplifiers like LM358 series have a common mode input voltage range of 0V to VDD-2V over temperature. In this case, 1V to 2.5V is a reasonable range for VSETH and VSETL.

External Operational Amplifier Circuit Considering Soft Start and Loop Handover Figure 3-2 External Operational Amplifier Circuit Considering Soft Start and Loop Handover

Pull VSETL low when CH2 is shutdown (EN2 = low) or operating in boost mode (DIR2 = low). Similarly, pull VSETH low when CH2 is shutdown (EN2 = low) or operating in buck mode (DIR2 = high). The NAND gates fit this application well as shown in Figure 3-2.

When designing the resistor dividers, start from drawing 0.1mA from the VREF pin, Rb and Rt are found as,

Equation 1. R b = V S E T H 0.1 m A
Equation 2. Rt=VREF-VSETH0.1mA

The time constant of Rt, Rb and Ct determines the soft start time,

Equation 3. t S S ≈ 2 R b R t × C t

where Rb||Rt is the parallel resistance of Rb and Rt,

Equation 4. R b R t = R b × R t R b + R t

In this example, 2V reference voltage is selected. Rb = 15kΩ and Rt = 20kΩ are selected.

With the soft start time of 10ms, Ct is found as,

Equation 5. Ct=tSS2RbRt=583nF

A 560nF cap is selected.

2N7002 is selected to discharge Ct. RLIM = 10Ω is selected to limit the peak current through the MOSFET.