SDAA145 Application note

SDAA145 October 2025 TPSI31P1-Q1

3.2 Active Pre-charge Controller

The TPSI31P1-Q1 functions as an active pre-charge controller with 17V isolated gate driver and bias supply. When combined with external power switches, power inductor, and diode, this constitutes an active pre-charge design. Compared to the TPSI3050-Q1, the TPSI31P1-Q1 incorporates two additional features specifically designed for pre-charge applications.

The inductor current undergoes continuous monitoring and control in a hysteretic operational mode to linearly charge the substantial capacitance of the DC-link capacitor.
This integrates a communication back-channel that transmits status information from the secondary side to the primary side to indicate power status on the secondary side.

Figure 3-2 shows the block diagram of this application. The TPSI31P1-Q1 receives control signals via the EN input from a microcontroller. The external power inductor (L1), in conjunction with power diode (D1) and power FET (M1), forms a bulk converter. M2 represents an optional MOSFET for reverse blocking functionality. The shunt resistor facilitates current monitoring in L1 through voltage measurement at the IS+ pin.

Figure 3-2 Block Diagram of TPSI31P1-Q1 in Application

The key operational feature is the buck converter configuration. When IS+ falls below VREF-, VDRV is asserted high to activate M1, initiating the energy storage cycle of the buck converter. When IS+ exceeds VREF+, VDRV is asserted low to deactivate M1, commencing the power transfer cycle of the buck converter. This process continues throughout the entire pre-charge cycle to regulate the charging current.

Suppose the HV battery is 800V, the DC-link capacitance is 1000uF, the pre-charge time requirement is 150ms. The average charging current can be computed as follows:

Equation 6.

I_{A V G} \geq \frac{C \times V_{B A T}}{t} = 5.33 A

The shunt resistor required to set the inductor current can be calculated:

Equation 7.

R_{S N S} \leq \frac{V_{R E F +} + V_{R E F -}}{2 \times I_{A V G}} = 130 m Ω

The maximum inductor current is:

Equation 8.

I_{P E A K} = \frac{V_{R E F +}}{R_{S N S}} = 9.46 A

The minimum inductor current is:

Equation 9.

I_{M I N} = \frac{V_{R E F -}}{R_{S N S}} = 1.23 A

The maximum switching frequency occurs when the voltage across the link capacitance reaches the midpoint value, which can be determined by the minimum power transfer capability of TPSI31P1, the total gate charge of the FET, and the gate-to-source voltage. Suppose P = 55mW, Vgs=15V, Qg = 14nC, the maximum switching frequency is:

Equation 10.

f_{M A X} = \frac{P}{V_{gs} \times Q_{g}} = 261.9 k H z

Based on the maximum switching frequency, the minimum inductance can be calculated:

Equation 11.

L_{M I N} \geq \frac{V_{B A T}}{4 \times f_{M A X} \times (I_{P E A K} - I_{M I N})} = 92.8 μ H

Therefore, 100uH inductance value can be selected. The C_DIV1 and C_DIV2 capacitors depends on the VDDH drop requirement. For example, the total capacitance formed by the series combination of C_DIV1 and C_DIV2 must result in 0.5V drop of VDDH supply rail:

Equation 12.

C_{D I V 1} ∥ C_{D I V 2} \geq \frac{Q_{G}}{∆ V} = 28 n F

To reduce the voltage drop further, the capacitance can be selected as C_DIV1 = 330nF, C_DIV2 = 1µF .

The TPSI31P1-Q1 includes a calculator that incorporates these equations and generates the anticipated charging waveform. For additional details, see TPSI31P1-CALC.