Stitching vias can improve signal integrity, reduce impedance and inductance, minimize noise and crosstalk, and also enhance EMI shielding. The EMC test boards employ stitching vias for several different purposes, including:

Enhancing high speed signal integrity and reliability:

The serial clock signal required by many ADCs can be as high as 50MHz. Stitching vias can significantly enhance signal integrity and reliability for high-speed signals by providing a low impedance ground return path, reducing ground ringing and crosstalk. Keep high-speed signals on the same layer as the ADC if possible. Use a single stitching via or stitching via array if a high-speed signal must be routed between different layers. Figure 1-26 shows the side view of a stitching via on a 4-layer circuit board.

Figure 1-26 Side View of Stitching Via for High-Speed Signal

The EMC test boards route the SCLK trace on the top layer between the ADC and the digital isolator. The SCLK trace then continues from the digital isolator and connector J1 to the controller board on the top layer. Therefore, this design does not require stitching vias for the SCLK signal. Figure 1-27 shows stitching via examples for the DIN and DOUT signals on the RTD EMC test boards.

Figure 1-27 Stitching Vias for Signals.

Layer transition and ground pour connection:

Use stitching vias transitioning between layers to improve signal integrity by providing a consistent reference plane and a low impedance return path for signals. Stitching vias are also used to connect ground pours across multiple layers and ensure minimum impedance for any return current propagating along the PCB reference plane. Figure 1-28 shows the layer transition and ground connection design example on the 2-layer RTD EMC test board.

Figure 1-28 Stitching Vias for Layer Transition and Ground Connection.