SDAA175 November   2025 AM62A3 , AM62A7 , AM67A , TDA4VM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2C7xMMA Cache Structure
  6. 3Model DDR Read/Write Analysis for a Compiled TIDL Model
  7. 4Model Optimization
    1. 4.1 Simple Structure Models
    2. 4.2 Complex Structure
      1. 4.2.1 Residual Structures
      2. 4.2.2 Parallel Branch Merge
  8. 5Summary
  9. 6References

Simple Structure Models

Simple models have linear, non-branching structures. The initial section of EfficientNet shown below is entirely sequential. Here, ensuring each layer’s output fits within L3 suffices. TIDL can automatically configure layers to run using L3, avoiding DDR interaction. DDR interaction will still be required when intermediate feature maps are larger than the L3 size.

 Simple Model with Sequential
                    Layer Ordering Figure 4-1 Simple Model with Sequential Layer Ordering