Product details


Arm CPU 2 ARM Cortex-A72 Arm MHz (Max.) 1800 DSP 1 C7x, 2 C66x DSP MHz (Max) 1350, 1000 Graphics processing unit (GPU) 1 GE8430 2D/3D GPU frequency (Max) (MHz) 750 Hardware accelerators 1 Deep Learning accelerator, 1 Depth and Motion accelerator, 1 Video Encode/Decode accelerator, 1 Vision Processing accelerator Co-processor(s) MCU island: 2 ARM Cortex-R5F (lockstep opt), SoC main: 4 ARM Cortex-R5F (lockstep opt) Features MCU island: ASIL-D, SoC main: ASIL-B Security Cryptographic acceleration, Debug security, Device identity, Isolation firewalls, Secure boot & storage & programming, Software IP protection, Trusted execution environment Other on-chip memory 9.5 MB EMIF 1 32-bit DRAM LPDDR4-3733 Storage interface 1 2L UFS, 1 eMMC, 2 SDIO SPI 1 OSPI/HyperBus, 1 QSPI, 11 McSPI CSI-2 4L TX, 8L RX Display type 2 DPI, 1 DSI, 1 EDP Ethernet MAC 8-port 2.5Gb switch PCIe 4 PCIe Gen3 Serial I/O I2C, I3C, UART, CAN-FD, USB Rating Automotive open-in-new Find other TDAx ADAS SoCs

Package | Pins | Size

FCBGA (ALF) 827 open-in-new Find other TDAx ADAS SoCs


  • Processor cores:
  • C7x floating point, vector DSP, up to 1.0 GHz, 80 GFLOPS, 256 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 1.8 GHz, 22K DMIPS
    • 1MB shared L2 cache per dual-core Cortex®-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 core
  • Six Arm® Cortex®-R5F MCUs at up to 1.0 GHz, 12K DMIPS
    • 64K L2 RAM per core memory
    • Two Arm® Cortex®-R5F MCUs in isolated MCU subsystem
    • Four Arm® Cortex®-R5F MCUs in general compute partition
  • Two C66x floating point DSP, up to 1.35 GHz,
    40 GFLOPS, 160 GOPS
  • 3D GPU PowerVR® Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec
  • Custom-designed interconnect fabric supporting near max processing entitlement
  • Memory subsystem:
  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 3733 MT/s
    • 32-bit data bus with inline ECC up to 14.9GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC
  • Safety: targeted to meet ASIL-D for MCU island and ASIL-B for main processor
  • Integrated MCU island subsystem of Dual Arm® Cortex®-R5F cores with floating point coprocessor and optional lockstep operation, targeted to meet ASIL-D safety requirements/certification
    • 512B Scratchpad RAM memory
    • Up to 1MB on-chip RAM with ECC dedicated for R5F
    • Integrated Cortex®-R5F MCU island isolated on separate voltage and clock domains
      • Dedicated memory and interfaces capable of being isolated from the larger SoC
  • The TDA4VM main processor is targeted to meet ASIL-B safety requirements/certification
    • Widespread ECC protection of on-chip memory and interconnect
    • Built-in self-test (BIST) and fault-injection for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Safety documentation available for applications required to meet ISO 26262 requirements
  • Device security:
  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
  • High speed serial interfaces:
  • Integrated ethernet switch supporting
    (total of 8 external ports)
    • Up to eight 2.5Gb SGMII
    • Up to eight RMII (10/100) or RGMII (10/100/1000)
    • Up to two QSGMII
  • Up to four PCI-Express® (PCIe) Gen3 controllers
    • Up to two lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 Ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD
  • Automotive interfaces:
  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Capture subsystem:
  • Two CSI2.0 4L RX plus One CSI2.0 4L TX
    • 2.5Gbps RX throughput per lane (20Gbps total)
  • Display subsystem:
  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI
  • Audio interfaces:
  • Twelve Multichannel Audio Serial Port (MCASP) modules
  • Video acceleration:
  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode
  • Flash memory interfaces:
  • Embedded MultiMediaCard Interface (eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital® 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or HyperBus™ and QSPI flash interface
  • System-on-Chip (SoC) architecture:
  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing
  • TPS6594-Q1 Companion Power Management ICs (PMIC):
  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

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The TDA4VM processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to 4 Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.

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Sample availability

ALF package is in preview. Preproduction samples for XTDA4VMXXXGALF are available (symbolized XJ721EGALF).  Request now

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 20
Type Title Date
* Datasheet TDA4VM Jacinto™ Automotive Processors for ADAS and Autonomous Vehicles Silicon Revision 1.0 datasheet (Rev. E) Dec. 15, 2019
* User guide DRA829/TDA4VM/AM752x Technical Reference Manual (Rev. A) Nov. 14, 2019
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors Oct. 22, 2020
Application note OSPI Tuning Procedure Jul. 08, 2020
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. A) Apr. 23, 2020
White paper 360度環景系統與自動停車系統 Mar. 01, 2020
White paper 360도 인식이 가능한서라운드뷰와 자동 주차 시스템 Mar. 01, 2020
White paper 運用 Jacinto™ 7 處理器的汽車設計功能安全特性 Mar. 01, 2020
White paper 오토모티브 설계 시 Jacinto™ 7 프로세서의 기능적 안전성 활용하기 Mar. 01, 2020
Technical articles Making ADAS technology more accessible in vehicles Jan. 07, 2020
White paper Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs Dec. 12, 2019
White paper A 360-degree view of surround-view and automated parking systems Dec. 10, 2019
More literature Jacinto 7 EVM Quick Start Guide for TDA4VM and DRA829V Processors Oct. 10, 2019
Application note Jacinto 7 High-Speed Interface Layout Guidelines Oct. 04, 2019
User guide C6000-to-C7000 Migration User's Guide (Rev. C) Aug. 11, 2019
User guide VCOP Kernel-C to C7000 Migration Tool User's Guide (Rev. C) Aug. 11, 2019
User guide User's Guide for Powering DRA829V and TDA4VM with the TPS6594-Q1 PMICs Jul. 09, 2019
Technical articles Smart sensors are going to change how you drive (because eventually, you won’t) Apr. 25, 2018
Technical articles AI in Automotive: Practical deep learning Feb. 08, 2018
Technical articles How to maintain automotive front camera thermal performance on a hot summer day Feb. 02, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The J721EXCP01EVM common processor board for Jacinto™ 7 processors lets you evaluate vision analytics and networking applications in automotive and industrial markets. The common processor board is compatible with all Jacinto 7 processors system-on-modules (sold separately or as a (...)

  • UFS flash memory, 32GByte, 2Lane, Gear3
  • USB3.1 type C interface, support DFP, DRP, UFP modes
  • Display port, up to 4K resolution with MST support
  • 2x PCIe card slot, 1x PCIe M.2 slot (M‐Key), all Gen3

The J721EXSOMG01EVM system-on-module—when paired with the J721EXPCP01EVM common processor board—lets you evaluate TDA4VM and DRA829V processors in vision analytics and networking applications throughout automotive and industrial markets. These processors perform (...)

  • TDA4VM/DRA829V (J721 E) processor
  • Optimized power solution (PMIC)
  • DRAM, LPDDR4‐3733, 4GByte total memory, support inline ECC
  • Octal‐SPI NOR flash, 512Mb memory (8bit)
  • HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

  • Ethernet
    • 4x 10/100/1000Mbps - RGMII ports (DP83867E)
    • 1x 10/100Mbps - RMII port (DP83822I)
  • 6x CAN interface
  • 6x LIN interface
  • PROFI BUS/RS485 port (DB9)
  • USS/IMU sensor header
  • Motor control header
  • Booster pack interface header
  • Board ID EEPROM
Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
  • Audio interfaces:
    • Two Audio codecs each with three Stereo Inputs and four Stereo Outputs
    • Audio input over FPD Link III
    • Digital Audio Interface Transmit
    • Digital Audio Interface Receiver
  • Video interfaces:
    • HDMI/FPD LINK III Display out
    • LI/OV Camera input
  • JAMR3 interface
  • Board ID EEPROM

The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all ARM and (...)


The XDS110 is the latest entry level debug probe (emulators) for TI embedded processors. Designed to be a complete solution that delivers JTAG and SWD connectivity at a low cost, the XDS110 is the debug probe of choice for entry-level debugging of TI microcontrollers, processors and SimpleLink (...)


The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)


XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

D3 Engineering RVP-TDAx development kits
Provided by D3 Engineering
These rugged development kits are in a finalized product form-factor that lets you evaluate TI ADAS technology under realistic on-vehicle conditions. Accelerate development of autonomous vision-based navigation systems for automotive, transportation and materials handling applications. The (...)

Software development

Software Development Kit for DRA8x & TDA4x Jacinto™ processors
PROCESSOR-SDK-DRA8X-TDA4X — Depending on the device selection, Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for TDA4x and DRA8x SoCs within TI’s Jacinto™ platform (...)
  • Detailed feature lists for each SDK can be found in the respective release notes links found on the SDK download pages.
Hella Aglaia TDAx-based ADAS algorithms for front camera
Provided by Hella Aglaia HELLA Aglaia develops embedded software solutions for advanced driver assistance systems – compliant with certified industry standards and ready for hardware integration.

Leveraging the powerful deep learning capabilities of the TDA4x processor family, HELLA Aglaia’s robust image processing (...)

Momenta deep learning algorithms for ADAS forward camera applications on TDA4x processors
Provided by Momenta Momenta’s deep learning based algorithms for ADAS applications make full use of the DSP cores and accelerators on TDA4x for neural network processing. Designed to achieve market leading computational and power efficiency, Momenta’s algorithms offer an array of pre- and post-imaging (...)
Wind River Processors VxWorks and Linux operating systems
Provided by Wind River Systems Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
Code Composer Studio (CCS) Integrated Development Environment (IDE)

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

QNX Neutrino RTOS
Provided by QNX Software Systems — The QNX Neutrino® Realtime Operating System (RTOS) is a full-featured and robust RTOS designed to enable the next-generation of products for automotive, medical, transportation, military and industrial embedded systems. Microkernel design and modular architecture enable customers to create (...)

Design tools & simulation

SPRM751.ZIP (13 KB) - BSDL Model
SPRM752.ZIP (1983 KB) - IBIS Model
SPRM753.ZIP (1 KB) - Thermal Model
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
Pin mux tool
PINMUXTOOL The PinMux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or (...)

CAD/CAE symbols

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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