Next generation SoC family for L2/L3, near-field analytic systems using deep learning technologies
Product details
Parameters
Package | Pins | Size
Features
Processor cores:
- C7x floating point, vector DSP, up to 1.0 GHz, 80 GFLOPS, 256 GOPS
- Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
- Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 1.8 GHz, 22K DMIPS
- 1MB shared L2 cache per dual-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
- Six Arm Cortex-R5F MCUs at up to 1.0 GHz, 12K DMIPS
- 16K I-Cache, 16K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Four Arm Cortex-R5F MCUs in general compute partition
- Two C66x floating point DSP, up to 1.35 GHz, 40 GFLOPS, 160 GOPS
- 3D GPU PowerVR Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec
- Custom-designed interconnect fabric supporting near max processing entitlement
Memory subsystem:
- Up to 8MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- External Memory Interface (EMIF) module with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 3733 MT/s
- 32-bit data bus with inline ECC up to 14.9GB/s
- General-Purpose Memory Controller (GPMC)
- 512KB on-chip SRAM in MAIN domain, protected by ECC
Functional Safety:
- Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
- Systematic capability up to ASIL-D/SIL-3 targeted
- Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
- Safety-related certification
- ISO 26262 planned
Device security:
- Secure boot with secure runtime support
- Customer programmable root key, up to RSA-4K or ECC-512
- Embedded hardware security module
- Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
- Integrated ethernet switch supporting (total of 8 external ports)
- Up to eight 2.5Gb SGMII
- Up to eight RMII (10/100) or RGMII (10/100/1000)
- Up to two QSGMII
- Up to four PCI-Express (PCIe) Gen3 controllers
- Up to two lanes per controller
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
- Two USB 3.0 dual-role device (DRD) subsystem
- Two enhanced SuperSpeed Gen1 Ports
- Each port supports Type-C switching
- Each port independently configurable as USB host, USB peripheral, or USB DRD
Automotive interfaces:
- Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
- Two CSI2.0 4L RX plus One CSI2.0 4L TX
- 2.5Gbps RX throughput per lane (20Gbps total)
Display subsystem:
- One eDP/DP interface with Multi-Display Support (MST)
- HDCP1.4/HDCP2.2 high-bandwidth digital content protection
- One DSI TX (up to 2.5K)
- Up to two DPI
Audio interfaces:
- Twelve Multichannel Audio Serial Port (MCASP) modules
Video acceleration:
- Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
- Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
- Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode
Flash memory interfaces:
- Embedded MultiMediaCard Interface ( eMMC™ 5.1)
- Universal Flash Storage (UFS 2.1) interface with two lanes
- Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
- Two simultaneous flash interfaces configured as
- One OSPI and one QSPI flash interfaces
- or HyperBus™ and QSPI flash interface
System-on-Chip (SoC) architecture:
- 16-nm FinFET technology
- 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
- Functional Safety support up to ASIL-D
- Flexible mapping to support different use cases
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Description
The TDA4VM processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview
The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.
General Compute Cores and Integration Overview
Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.
Sample availability
ALF package is in preview. Preproduction samples for XTDA4VMXXXGALF are available (symbolized XJ721EGALF). Request now
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The J721EXCP01EVM common processor board for Jacinto™ 7 processors lets you evaluate vision analytics and networking applications in automotive and industrial markets. The common processor board is compatible with all Jacinto 7 processors system-on-modules (sold separately or as a (...)
Features
- UFS flash memory, 32GByte, 2Lane, Gear3
- USB3.1 type C interface, support DFP, DRP, UFP modes
- Display port, up to 4K resolution with MST support
- 2x PCIe card slot, 1x PCIe M.2 slot (MâKey), all Gen3
Description
The J721EXSOMG01EVM system-on-module—when paired with the J721EXPCP01EVM common processor board—lets you evaluate TDA4VM and DRA829V processors in vision analytics and networking applications throughout automotive and industrial markets. These processors perform (...)
Features
- TDA4VM/DRA829V (J721 E) processor
- Optimized power solution (PMIC)
- DRAM, LPDDR4â3733, 4GByte total memory, support inline ECC
- OctalâSPI NOR flash, 512Mb memory (8bit)
- HyperFlash + HyerRAM, 512Mb flash memory + 256Mb RAM
Description
Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.
Features
- Ethernet
- 4x 10/100/1000Mbps - RGMII ports (DP83867E)
- 1x 10/100Mbps - RMII port (DP83822I)
- 6x CAN interface
- 6x LIN interface
- PROFI BUS/RS485 port (DB9)
- USS/IMU sensor header
- Motor control header
- Booster pack interface header
- Board ID EEPROM
Description
Features
- Audio interfaces:
- Two Audio codecs each with three Stereo Inputs and four Stereo Outputs
- Audio input over FPD Link III
- Digital Audio Interface Transmit
- Digital Audio Interface Receiver
- Video interfaces:
- HDMI/FPD LINK III Display out
- LI/OV Camera input
- JAMR3 interface
- Board ID EEPROM
Description
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
Features
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
Description
Software development
Features
- Detailed feature lists for each SDK can be found in the respective release notes links found on the SDK download pages
Leveraging the powerful deep learning capabilities of the TDA4x processor family, HELLA Aglaia’s robust image processing (...)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)
Features
By Platform - Find out more about the features available for a specific processor family:
Design tools & simulation
- Visualize the device clock tree
- Interact with clock tree elements (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
FCBGA (ALF) | 827 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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