SDAA203 November   2025 AFE7920

 

  1.   1
  2.   Abstract
  3. 1Introduction
  4. 2Issue Phenomenon and Observations
  5. 3Introduction to Phase Locked Loop (PLL)
  6. 4Design
  7. 5Summary
  8. 6References

3 Introduction to Phase Locked Loop (PLL)

A black background with white rectangles and black text AI-generated content may be incorrect. Figure 3-1 Generic Block Diagram of AFE PLL

A phase-locked loop (PLL) consists of a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and an N divider. The problematic part of this issue is the range of Vctrl that comes from the LPF output and is connected to the VCO input.

To verify the lock across temperature during calibration the Vctrl voltage has to be set to a reference target voltage (V]ref). This Vref is a voltage that scales linearly with temperature and is trimmed on ATE. Vref is a reference voltage while Vctrl is the tuning voltage for VCO of PLL. During the initial PLL calibration step at bring up, the cap bank in VCO is adjusted such that the VCO outputs desired frequency when Vctrl = Vref. Offsetting by 200mV in the Vref offsets Vctrl by 200mV. Offsetting Vref is only a functional fix to make sure that the PLL locks across temperature and does not affect the performance of the AFE.