SDAA206A March 2026 – May 2026 TAS2781
| Pin Number | Pin Name | Schematic Considerations | Layout Considerations | ||
|---|---|---|---|---|---|
| TAS2783A/TAS2785 | TAS2781 | ||||
| 28 | PVDDH | PVDDH | Connect to 3s, 4s battery or boost converter
output Decouple to GND with 10uF+10uF+0.1uF at 25V |
Use a wide trace to handle the high current
Place the capacitors as close to the device pin as possible Make sure there is a short ground return path to pin 2, PGND. if no top layer GND plane is used. Pour a polygon around the ground side of the capacitors and use many vias to give a low impedance ground return path through layer 2. |
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| 27 | PVDDL | PVDDL | PWR_MODE0,1,3 connect to 1s battery, or 2.7V5.5V DC-DC Decouple to GND with 10uF+0.1uF at 10 PWR_MODE2 Do not connect externally to a voltage Decouple to GND with 1uF+0.1uF at 6.3V |
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| 24 | AVDD | AVDD | Connect to 1.8V Decouple to GND with 4.7uF at 6.3V |
Place the capacitor as close to the pin 24 as possible. Connect the ground side of the capacitor to pin 25 on the top layer | |
| 20 | IOVDD | IOVDD | TAS2781 Connect to 1.8V or 3.3V Decouple to GND with 1uF at 6.3V Rated. TAS2783A/TAS2785 Connect to 1.2V, 1.8V or 3.3V Decouple to GND with 2.2uF at 6.3V |
Note: if Pin 17 and Pin 20 are sharing a supply voltage, the pins can be shorted together and a single 2.2uF capacitor can be used. This applies to TAS2781 and TAS2783A and TAS2785 | Place decoupling capacitors near device pin. Short ground side of the cap to the layer 2 ground plane with a via |
| 17 | IOVDD-SDW | NC_V1P8V | If pin 6,8,9 are used, ICC, SPI or Soundwire are used TAS2781 Connect to 1.8V Decouple to GND with 1uF at 6.3V. TAS2783A/TAS2785 Connect to 1.2V or 1.8V Decouple to GND with 2.2uF at 6.3V |
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| 10 | DREG | DREG | Decouple to GND with 1uF at 6.3V Do not connect externally to a supply or load |
Place directly next to the device pin. There must be a short, direct, and low impedance path to pin 7 GND. Use vias on the ground side of the capacitor to layer 2 GND | |
| 1, 5 | VSNSN & VSNSP | VSNSN & VSNSP | Short to the speaker output after any LC Filter. Use 2.2kΩ 1% resistor in series | Route differentially and connect to the speaker connector. The 2.2kΩ resistor placement is not critical. This trace carries no current. It can be as thin as allowed by the PCB fab. | |
| 3,29 | OUTP and OUTN | OUTP and OUTN | This is a filter less class-D. LC filter is optional and only for EMI purposes. Use 120Ω ferrite bead and shunt 1nF capacitor if a filter is required. | Route with wide traces to the speaker connection. Make VSNS connections as close to the speaker as possible. Keep the route short and place the EMI filter near the device to limit emissions. | |
| 4,30 | BSTP and BSTN | BSTP and BSTN | Place a 100nF 10V capacitor between BSTP<->OUTP and BSTN<->OUTN. Connect the capacitor before any LC Filter. | Both sides of this capacitor must have a low impedance connection. The capacitors can be placed on the bottom side of the PCB. | |
| 26 | MODE | MODE | Short to AVDD - Soundwire Mode Short to GND - I2C Mode 470 to GND - SPI Mode |
Not critical. Do not allow mode pin connection to affect the AVDD routing. | |
| 23 | ADDR | ADDR | Short to GND - SNDW UID 0x08 OR I2C Address
0x70 470Ω to GND - SNDW UID 0x09 OR I2C Address 0x72 470Ω to AVDD - SNDW UID 0x0A OR I2C Address 0x74 2.2kΩ to GND - SNDW UID 0x0B OR I2C Address 0x76 2.2kΩ to AVDD - SNDW UID 0x0C OR I2C Address 0x78 10kΩ to GND - SNDW UID 0x0D OR I2C Address 0x7A 10kΩ to AVDD - SNDW UID 0x0E OR I2C Address 0x7C Short to AVDD - SNDW UID 0x0F OR I2C Address 0x7E |
Not Critical. Do not allow ADDR pin connection to affect the AVDD routing. | |
| 11 | PWM_CTRL | PWM_CTRL | Connect to LC filter then boost feedback pin. Refer to {link to sloa326} for design guidance on the Class-H boost. Leave floating if unused | Not critical | |
| 21 | IRQz | IRQz | In I2C or SPI Modes Pull up to IOVDD with 20kΩ . Connect to SoC GPIO to monitor device interrupt In SNDW Mode Pull up to IOVDD with 20kΩ even if unused. |
Not critical | |
| 22 | SDz | SDz | Connect to the SoC GPIO | Not critical | |
| 25,2,7 | DGND, PGND, GND | DGND, PGND, GND | Short to board ground | Place a ground polygon under the device package on the top layer.
Short pins 2,7, and 25 to this polygon, and use multiple vias to
short that polygon to the Layer 2 GND plane The Layer directly under the top layer must be dedicated to ground. |
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| 16 | NC | NC | Short to board ground | Not critical | |
| 6 | SWDATA1 | ICC | I2C/SPI Modes Short ICC between two L and R channel devices Float if unused Soundwire mode (TAS2783A/TAS2785) Connect to the host data lane 1 Short to GND if unused |
In Soundwire mode Control the impedance to 50Ω Length match the trace segments of clock and data between Host <-> Device, and Device <-> Device Do not route near any high current or switching signals, such as PVDDH, PVDDL, OUTP, OUTN, BSTP, BSTN,VSNSP,VSNSN |
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| 8 | SWDATA0 | NC_SDO | SPI Mode Connect to host SPI data in Soundwire mode Connect to the host data lane 0Short to ground if unused |
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| 9 | SWCLK | NC_SCLK | SPI Mode Connect to host SPI clock output Soundwire mode Connect to host Soundwire clock output |
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| 18 | SCL | SCL_nSCS | I2C Mode Pull up to IOVDD with resistor SPI Mode Connect to host SPI chip select Soundwire Mode Pull up to IOVDD even if unused |
Do not route near any high current or switching signals, such as PVDDH, PVDDL, OUTP, OUTN, BSTP, BSTN, VSNSP,VSNSN | |
| 19 | SDA | SDA_SDI | I2C Mode Pull up to IOVDD with resistor SPI Mode Connect to host SPI data output Soundwire Mode Pull up to IOVDD even if unused |
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| 12 | SDOUT | SDOUT | Connect to host Leave floating if unused |
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| 13,14,15 | SDIN, FSYNC, SBCLK | SDIN, FSYNC, SBCLK | Connect to host Connect to ground if unused |
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