SDAA252 Application note

Arc Fault Electrical Characteristics

Arc faults produce distinctive electrical signatures that differ from normal load operation:

Time-Domain Characteristics:

Current discontinuities at zero crossings (arc extinguishes when voltage drops)
Irregular current waveform with high-frequency noise superimposed
Current magnitude may be lower than normal load (series arcs)
Shoulder phenomenon: current shoulder near zero crossing as arc re-ignites

Frequency-Domain Characteristics:

Broadband noise from DC to tens of MHz
Time-varying pink noise spectrum (1/f roll-off)
Arc energy present across wide frequency range
Distinct spectral signature compared to normal switching transients

Figure 3-1 Normal Frequency Spectrum

Figure 3-2 Arc Fault Frequency Spectrum

Table 3-1 Arc Signature vs Load Noise

Characteristic	Arc Fault	Normal Load (Motor/Dimmer)
Temporal Pattern	Random, chaotic	Periodic, predictable
Zero-Crossing Behavior	Extinguishes/re-ignites	Smooth transitions
Energy Distribution	Uniform across spectrum	Concentrated at harmonics

Signal Processing Overview (TIDA-010971)

The TIDA-010971 implements a multichannel sensing strategy using a PCB Rogowski coil with >40 MHz bandwidth:

Table 3-2 Signal Channels

Channel	Frequency Range	Purpose	ML Feature Usage
Band-pass current	5-50kHz	Arc noise in audible/ultrasonic range	Primary input for FFT features
LOG300 HF output	1-10MHz	High-frequency arc energy	Arc energy magnitude
Low-pass current	DC-60Hz	Fundamental current magnitude	Load level detection
Line voltage	60 Hz	Zero-crossing reference	Phase synchronization

Key Design Concepts

For complete circuit schematics, component values, and design calculations, refer to the TIDA-010971 Design Guide.

PCB Rogowski Coil: Differential coil outputs di/dt signal; self-resonance >40MHz enables wideband arc detection
Hybrid Integrator: TLV387-based circuit converts di/dt to current-proportional signal with 68.6 dB gain
LOG300 Detector: Provides 98 dB dynamic range for MHz-frequency arc energy detection

Feature Extraction Pipeline

The firmware extracts frequency-domain features from raw ADC samples:

Figure 3-3 Feature Extraction Pipeline

Timing Relationships

ADC sampling interval: 9.3µs (1/107 kHz approximately 9.3µs)
Frame period: 512 samples × 9.3µs equals approximately 4.76ms
Rolling window: 8 frames × 4.76ms equals approximately 38ms of temporal context
Inference rate: Once per frame (approximately 4.76ms)

Configuration Parameters (user_input_config.h):

Note: Note on Rolling Window: The term "window" here refers to the temporal sliding window of eight consecutive frames, not an FFT window function (for example, Hanning, Hamming). Each new frame shifts the window forward, providing continuous temporal context for arc detection.

#define FE_FRAME_SIZE 512             // ADC samples per frame
#define FE_FEATURE_SIZE_PER_FRAME 32  // Output features per frame
#define FE_NUM_FRAME_CONCAT 8         // Frames in rolling window
#define FE_BIN_SIZE 8                 // FFT bins per feature bin
#define FE_BIN_OFFSET 1               // Skip DC component
#define FE_COMPLEX_MAG_SCALE_FACTOR 5 // Magnitude scaling

Processing Steps:

Real FFT: 512-point FFT using ARM CMSIS-DSP (arm_rfft_q15)
Complex Magnitude: Calculate magnitude of each frequency bin
DC Removal: Skip DC component (FE_BIN_OFFSET = 1)
Binning: Average 8 adjacent FFT bins → 32 features
Normalization: Scale to INT8 range (-128 to 127)
Frame Concatenation: Stack eight frames in rolling window → 256 total features

Processing Steps

ML Model Architecture

To support a wide range of memory, latency, and accuracy requirements on MSPM0-class devices, the Arc Fault Detection solution provides a family of lightweight convolutional neural network (CNN) models. These models share a common 3-layer convolutional backbone and differ only in channel depth, allowing scalable deployment from ultra-low-footprint to higher-accuracy configurations. The neural network classifies the extracted features as arc fault or normal.

Table 3-3 Model Architecture Comparison NOTE: The performance metrics below are measured for an input dimension of N=1, C=1, H=256, W=1

Model Name	Parameter	Flash Size (B)	SRAM Size (B)	Inference Time	Accuracy	Recommendation
ArcFault_model_200_t	~200	3652	900	197.82us	99.60%	Simplest, smallest and fastest model.
ArcFault_model_300_t	~300	3864	1644	246.91 us	99.60%	Faster than the 700 and 1400 variant, but also handles less complex data.
ArcFault_model_700_t	~800	4496	1644	288.36 us	99.42%	Large model, sweet spot between inference speed and memory occupied.
ArcFault_model_1400_t	~1600	5564	2408	713.31 us	99.88%	Most accurate model, use for complex data scenarios (Recommended)

The Arc Fault models mentioned above are proprietary and hence are only available in the GUI Based EdgeAI Studio.

Figure 3-4 Recommended 1D CNN Architecture for Arc Fault Detection. Recommended 1D CNN architecture for arc fault detection (Arc Fault Model 1400t model)

NPU Acceleration

The MSPM0G5187 includes an integrated TinyEngine™ NPU that accelerates neural network inference:

NPU Features:

Hardware acceleration for common NN operations
Instruction and parameter memory for model storage
Interrupt-driven completion signaling
TVM runtime integration via TI Neural Network Compiler (TI-NNC)

Integration with TI-NNC

The TI Neural Network Compiler generates:

model.a: Compiled model library
tvmgen_default.h: C interface header
user_input_config.h: Feature extraction configuration

3 Technical Background