SDAA254 August   2026 TAS5431-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TAS5431-Q1 Load Diagnostics
    1. 2.1 Types of Load Faults Detected
    2. 2.2 Diagnostic Sequence, Timing, and Fault Response
    3. 2.3 Register Reporting
    4. 2.4 Measuring the Load Diagnostics Waveform Using an Oscilloscope
    5. 2.5 Troubleshooting Load Diagnostics Through Software
    6. 2.6 Application-Level Considerations
  6. 3Summary
  7. 4References

Diagnostic Sequence, Timing, and Fault Response

The load diagnostic sequence occurs under these conditions:

  • On de‑assertion of the STANDBY pin
  • Immediately following fault recovery from DC detect, overcurrent, overvoltage*, undervoltage, or overtemperature events

*Note, load diagnostics run after every two overvoltage (OV) events

The test sequence consists of four phases totaling approximately 229ms, assuming no fault is present:

  1. Discharge phase (~75 ms)
  2. Ramp up (~52 ms)
  3. Check (~50 ms)
  4. Ramp down (~52 ms)

During the check phase, 10mA is sourced through the load from OUTP to OUTM, and the differential voltage is measured to determine the state of the load. See the TAS5431-Q1 datasheet for specifications on the load diagnostics fault detection thresholds.

Upon completion of a load diagnostics sequence in which no faults are detected, the audio output starts. If a fault is detected, or if a large output capacitance exists, the check phase may repeat up to five times, resulting in a maximum duration of approximately 429ms for a single load diagnostics sequence. The response to the fault depends on the type of fault that is present:

Open Load:

  • Audio remains enabled.
  • Only fault register status is updated.

Shorted load, short-to-PVDD, short-to-GND:

  • Output is forced into Hi-Z state
  • Load diagnostics repeat indefinitely until fault is cleared
  • Fault register status is updated
  • FAULT pin is asserted

While the load diagnostics sequence is active, bit D5 of the Status and Load Diagnostic Register (0x02) is asserted. This bit does not get de-asserted until exiting the load diagnostic sequence and starting the audio output, either through passing the diagnostics check, or the detection of an open load. In the case of any other load diagnostics failure, the bit remains asserted the entire duration that the fault is present and the load diagnostics sequence is repeating.

If a fault unrelated to diagnostics (voltage fault, thermal fault, overcurrent fault) occurs during diagnostics, the device exits diagnostics early and it is possible this can result in a pop or a click on the speaker output.

Figure 2-1 summarizes the diagnostic sequence, timing, and fault response.

 Flow Diagram of Diagnostic Sequence, Timing,
                    and Fault ResponseFigure 2-1 Flow Diagram of Diagnostic Sequence, Timing, and Fault Response