3 System Description and Observed Error

During evaluation on the customer's board, an abnormal startup behavior was observed. The system failed to complete the startup sequence when the bump reduction feature was enabled (Figure 3-1). In contrast, normal startup operation was achieved after the bump reduction feature was disabled (Figure 3-2). Under the failed startup condition, a VOUT_UV protection event was logged by the controller.

Since the exact timing and condition of the undervoltage (UV) trigger could not be directly identified from external measurements, an emulated controller was utilized to further investigate the event. By monitoring the internal VDAC voltage of the emulated controller and reporting its status through SMBus Alert, the occurrence of the UV trigger was successfully confirmed.

As shown in Figure 3-1, the output voltage stalls after the first few PWM pulses, as the controller stops PWM pulses. The question then arises as to why the controller stops generating PWM pulses. In simulation it was observed that the issue was related to saturation (high negative value) of the controller integrator.

Position of integrator ( ${\tau }_{INT}$ ) in the control loop is shown in Figure 3-3. In GUI, it is expressed as Int Time Constant (Figure 3-4). However, during bump reduction, a different value of ${\tau }_{INT}$ is used, which is stored in reg location 0xCE<14:12> (not in GUI) and denoted as Int_low_TC. The final value of the time constant, is ${\tau }_{INT}\times G_{INT}$ as shown in .Table 3-1