SDAA334 October 2026 TPS61170
Figure 4-1 shows the experimental results (VIN: Ch4 in green with 5V/div, VOUT (+9V): Ch2 in light blue with 5V/div, VOUT (-9V): Ch3 in purple with 5V/div), demonstrating that both output voltages (9V and -9V) are properly regulated at an input voltage of 5V using D1. Since the internal MOSFET current limit of the TPS61170 is minimum 0.96A, the output load must be carefully considered to verify that this limit is not exceeded.
In addition, during initial startup, the output current is required not only to supply the output load but also to charge the output capacitors, resulting in a higher inductor current than that under normal steady-state operation.
Figure 4-1 Startup Waveforms with 5V Input Using D1Figure 4-2 shows the key voltage and current waveforms under steady-state operation (VSW: Ch4 in green with 5V/div, VOUT (9V): Ch2 in light blue with 5V/div, VOUT (-9V): Ch3 in purple with 5V/div, IL1: Ch1 in blue with 250mA/div). The 9V and -9V outputs are properly regulated, and the waveforms of VSW and inductor current of L1 are also operating normally at a switching frequency of 1.2MHz.
Figure 4-3 shows the waveforms when the TPS61170 is disabled, and this experimental waveform shows that both positive and negative output voltages turn off as the input voltage drops and reaches about 2.2V, which is the UVLO threshold voltage of the TPS61170.
Figure 4-2 Key Waveforms Under Steady-State Operation
Figure 4-3 Waveforms When the TPS61170 is DisabledFigure 4-4 shows the experimental results (VIN: Ch4 in green with 5V/div, VOUT (+9V): Ch2 in light blue with 5V/div, VOUT (-9V): Ch3 in purple with 5V/div) using D1 and D2 in this case. The both output voltages (+9V and -9V) are properly regulated at an input voltage of 5V, and this method provides more accurate VOUT_N as shown in the following waveform. Figure 4-5 shows the key waveforms when the TPS61170 is disabled with the same test conditions.
Figure 4-4 Startup Waveforms With 5V Input Using D1 + D4
Figure 4-5 Waveforms when the TPS61170 is disabledFigure 4-6 shows loop gain and phase margin for the both D1 and D1+D4 cases. As shown in the measured loop gain results, when only D1 is used, the crossover frequency is 31kHz and the phase margin is approximately 53 degrees. When D1 and D4 are used together, the crossover frequency is 27kHz and the phase margin is approximately 50 degrees. In both cases, stable frequency response characteristics are achieved.
Figure 4-6 Loop Gain and Phase Margin