3 Root Cause of Gate Ringing Issues

As shown in Figure 3-1, Boost switches when the LS MOS is switched off, and the HS MOS is switched on. At this point, there is a prominent dv/dt at the SW point, as indicated by the red dotted line:

This voltage change dv/dt creates a significant current through the body diode of the HS MOS and the parasitic capacitance Cgd of Q1, which can be calculated by Equation 1 :

This current creates a distinct voltage spike at Q1 Gate and Rg; see Equation 2:

When the HS MOS is switched on, it is constantly charged at the Q1 Gate, and this current first causes the HS MOS to slow down charging and even reverse the voltage. So, it can be seen from the blue dashed waveform that the Vgs is inverted first, then a large voltage spike will be formed, and when this voltage spike exceeds the Vgsth of the MOSFET, it causes Q1 to open prematurely, if Q2 is not completely shut off. The large current will directly break through the MOSFET.

As can be seen from Equation 1 and Equation 2, the way to reduce this risk is to reduce I, so this ringing on MOSFETs can be reduced by reducing Cgd and dv/dt, or by reducing the Rg appropriately.

This can typically be avoided in the design and in the selection of MOSFETs in the following ways:

1. In terms of layout design, a Kelvin connection can be employed for the gate-to-Source loop, as illustrated in the LM5125A-Q1 EVM layout design shown in Figure 3-2
   Figure 3-2 LM5125A-Q1 EVM HO-GND Kelvin Connection Design (Layer 5)
   Figure 3-3 LM5125A-Q1 EVM Source-SW Kelvin Connection Design (Layer 6)

   As shown in Figure 3-3, the loop design from the Gate to SW utilizes adjacent layers and employs an identical trace layout; this approach minimizes the loop area, thereby reducing induced parasitic inductance.

   Figure 3-4 PCB Stack-Up Depicting Switching Loop With Low Area Using Layers L1 and L2

   Figure 3-4 shows a side view to illustrate the concept of creating a low profile, self-canceling loop in a multilayer PCB structure. The L2 GND plane layer provides a tightly coupled current return path directly under the MOSFETs to the source terminals of Q2.

2. Select a higher device in Vgsth when selecting MOSFETs to raise the ringing voltage to the open threshold and reduce the risk.
3. Select the MOSFET with less Cgd/Cgs ratio.
4. Lower Rg appropriately.
5. Parallel capacitance between Gate and Source, artificially increasing Cgs. Additional continuity losses must be considered.

Above several ways, most of the recommendations have some limitations of MOSFETs in the design. So the simplest and most effective way is the parallel capacitance solution proposed by 5. This document provides recommendations on the design of gate ringing for LM5125A-Q1 and LM5126A-Q1 based on the results.