SDAA340 April   2026 LM5125-Q1 , LM51251A-Q1 , LM5125A-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2LM5125/6A-Q1 Gate Ringing Issues
  6. 3Root Cause of Gate Ringing Issues
  7. 4Design of Gate Ringing Issues
  8. 5Summary
  9. 6References

Design of Gate Ringing Issues

LM5125A-Q1 and LM5126A-Q1 are widely used in automotive external amplifiers. The test follows the design scenarios of the application as a reference, as the main test setup in Table 4-1

Table 4-1 Test Setup
Parameter Value
Input voltage 14.4V
Output voltage 35V
Switching frequency 400kHz
Inductor Lm 3.3µH
HS Rg 2.2Ω
LS Rg 10Ω
MOSFET NVMFS5C670NL

Based on the original design, 1nF, 1.5nF, 2.2nF, and 3.3nF capacitors connected in parallel with Q1 were tested, and gate ringing tests were conducted on the turn-on and turn-off processes of the high-side MOSFET.

  1. Original Design Test:
     Original Design Test Results (HS ON/LS OFF (Left), HS OFF/LS ON
                            (Right)) Figure 4-1 Original Design Test Results (HS ON/LS OFF (Left), HS OFF/LS ON (Right))
  2. HO+1nf:
     HO+1nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON
                            (Right) Figure 4-2 HO+1nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON (Right)
  3. HO+1.5nf:
     HO+1.5nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON
                            (Right) Figure 4-3 HO+1.5nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON (Right)
  4. HO+2.2nf:
     HO+2.2nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON
                            (Right) Figure 4-4 HO+2.2nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON (Right)
  5. HO+3.3nf:
 HO+3.3nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON (Right) Figure 4-5 HO+3.3nf Test Results: HS ON/LS OFF (Left), HS OFF/LS ON (Right)

The test results are summarized in Table 4-2

Table 4-2 Summary of Test Results
HO Status Design ON OFF
Original 1.1V 0.7V
HO+1nF 1V 0.7V
HO+1.5nF 0.7V 0.9V
HO+2.2nF 0.6V 0.6V
HO+3.3nF 0.4V 0.5V

Therefore, considering the additional losses and the impact on switching speeds, it is calculated by

External 1.5nF only increases the HO gate driver loss.

Equation 3. P=14V×1.5nF×5V×400kHz=42mW

TI recommends incorporating a provision for this capacitor during the design phase; this facilitates debugging and eliminates risk if issues such as gate ringing arise. of HO+1.5nF as shown in Figure 4-6

 Design of HS MOS Parallel 1.5nF Figure 4-6 Design of HS MOS Parallel 1.5nF

TI recommends another design.

 Design of HO and PNP
                    Design Figure 4-7 Design of HO and PNP Design

As shown in Figure 4-7, an alternative design approach involves incorporating a PNP transistor on the drive side of the high-side switch. This design serves to enhance noise immunity and prevent spurious turn-on. When the HO output is in the OFF state, the current is coupled to GND through the PNP transistor, thereby preventing the buildup of a gate-source voltage (Ugs). This common-base PNP pull-down configuration effectively suppresses coupled interference, thereby preventing the inadvertent activation of the HO output.