The output stage consists of the load-transient FET, a series gate resistor, and a 1mΩ ballast resistor. The schematic is shown in Figure 2-4. The input stage passes a control signal to the driver stage where it is buffered and then used to drive the load FET. The profile of the input signal, V_in, dictates the profile of the load transient event. The series resistor at the gate of the FET limits the gate voltage's slew rate and improves circuit stability [4]. The ballast resistor ensures current sharing is roughly equal when multiple FETs are used in parallel. For example, if the V_th of one FET is lower than the others, it will conduct more current. The resulting voltage across the ballast resistor reduces the gate overdrive voltage of that FET, thereby reducing its current and improving current sharing among the parallel FETs. This board supports paralleling output stages via the right-angle connectors on the right side of the board. Each output stage would include its respective gate resistor, load transistor, and ballast resistor.

The board layout is such that the board itself may be soldered onto the output capacitor bank of a power converter to minimize inductance (DUT output on the PCB top layer, and GND on bottom layer). This short connection reduces the interface impedance and allows for faster transients.

Figure 2-4 Output Stage Schematic