The internal HS of UCC256612 can only support 640V; this leads to two issues:

1. UCC256612 uses the input of HS pin for adaptive dead time control to optimize the system performance.
2. The internal bootstrap circuit can't drive the high side FET.

Figure 2-5 shows the proposed schematic for those issues. To lower the voltage on HS pin with good response time, use two capacitors as a voltage divider to cut SW voltage into half and send the slew rate of SW into HS pin for adaptive dead time control and prevent HS from being out of the voltage stress. Limit the capacitance values (such as 68pF) to lower the parasitic capacitance, which can degrade the slew rate of the SW node. Use another two ultra-fast diodes in parallel with the capacitors to make sure the HS pin closes to GND when the low side FET turns on. .

Figure 2-5 SW Node Detection and Driving Circuit

To drive the high side device, use an external isolated gate driver. UCC5350 provides 3KV_RMS isolated voltage, 10A peak current drive strength, and 100V/ns CMTI capability which fulfills this application. In the input stage, use the HO signal as IN+ input, and HB for VCC1, and another bootstrap circuit with 1.2KV diode from VCCP to SW node to support VCC2. In UCC256612, the LO turn on voltage, V_LOH is:

The V_VCCP is the voltage on VCCP pin and V_{DRV_ON} is the V_DS voltage on the driver when it turns on, and the maximum voltage is 0.3V. This is very close to the VCCP. This means the user can drive external SiC FETs if we set the VCCP voltage to be about 18V, and 12 to approximately 15V for traditional MOSFETs. For PMP4113 reference design, drive external SiC FET, and set the VCCP to be 18V, but the VCC1 and IN+ of UCC5350 must be lower than 15V in. In this case, a regulator was used which is designed by 2N7002 MOSFET and 15V Zener diode with 200KΩ bias resistor to limit the voltage stress to be 15V – V_TH with low consumption but keep 18V bootstrap in VCC2 to drive SiC FET directly.

For systems that cannot verify V_VCCP above 12V (such as wide output voltage range application), an additional external VDD UVLO protection circuit is recommended to verify reliable SiC FET gate drive operation.

Is there any possibility of making the high and low side FETs shoot through because of more propagation delay on the isolated gate driver? Because of the adaptive dead time control method in UCC256612, the slew rate detector detects the dead time between HO turn off and LO turn on. This dead time is copied and then applied to low-side MOSFET turn off and high-side MOSFET turn on. Figure 2-6 shows the timing diagram of the dead time detection. To simplify the problem, we set the total propagation delay time of high side turn off (including HO from high to low, and OUTL) is t_D. Assume the total propagation delay time of high side turn on is as the same value. Time between SW falling time, t_SWF to LO turn on with approximately 40ns detection delay time as t_DET. At this moment, the dead time from high side turn off to low side turn on, t_DEAD is:

Figure 2-6 Timing Diagram of Dead Time Detection Circuit

Calculate the real dead time from low side turn off to high side turn on to be t_DEAD + t_D. For the SW pin from high to low, the dead time is detected, and it is not possible to shoot through. For the SW pin from low to high, more time was extended to make sure the system is not overlapping. To reduce the dead time of SW pin from low to high, we may put another isolated gate driver to balance the turn off time on low side FET.

Figure 2-7 shows the waveform of LO turns on. t_SWF + t_DET is 216ns, and Figure 2-8 shows the waveform of LO turns off and the t_SWR = 161ns, which is shorter than the t_DEAD.

Figure 2-7 LO Turns On Waveform CH1: SW, CH3: LO, CH6: I_RES

Figure 2-8 LO Turns Off Waveform CH1: SW, CH3: LO, CH6: I_RES