SDAA560 October   2026 SN74UVP1G04 , SN74UVP1G04-Q1 , SN74UVP1G06 , SN74UVP1G06-Q1 , SN74UVP1G07 , SN74UVP1G07-Q1 , SN74UVP1G14 , SN74UVP1G14-Q1 , SN74UVP1G16 , SN74UVP1G16-Q1 , SN74UVP1G17 , SN74UVP1G17-Q1 , SN74UVP1G37 , SN74UVP1G37-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Applications
    2. 2.2 Power Consumption
    3. 2.3 Timing at Low Supply Voltage
    4. 2.4 Power-Up, Power-Down, and Ioff Behavior
  6. 3Summary
  7. 4References

1 Introduction

Single-gate logic devices are commonly used in wake, reset, enable, interrupt, and power-sequencing paths. These paths can remain powered even when the MCU, RF block, display, or primary system rail are disabled.

For these applications the key design requirements are:

  • Very low static supply current (ICC)
  • Reliable operation at the minimum system voltage
  • Valid input and output logic levels at low VCC
  • Predictable propagation delay at the minimum supply voltage
  • Safe behavior during power-up, power-down, and partial-power-down conditions

The SN74UVP family addresses all five requirements. While extending the minimum VCC from 0.8V to 0.63V, the SN74UVP family maintains a 3.6V maximum.

Table 1-1 Operating Voltage Range and Key Parameter Comparison
Logic FamilyMin VCCMax VCCMax VITypical ICC
Standard LV-CMOS (for example, LVC)1.65V5.5V5.5V1µA
SN74AUP (single channel)0.8V3.6V3.6V500nA
SN74UVP (single channel)0.63V3.6V5.5V10nA