SDAA565A October   2026  – October 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Architecture
    1. 2.1 EVM Configuration
    2. 2.2 APS6408L PSRAM Device
      1. 2.2.1 OSPI PSRAM Configurations
  6. 3Software Architecture
  7. 4Implementation Guide
    1. 4.1 Prerequisites
    2. 4.2 Example Applications
      1. 4.2.1 Secondary Bootloaders
        1. 4.2.1.1 SBL OSPI PSRAM
        2. 4.2.1.2 SBL SD PSRAM
      2. 4.2.2 OSPI PSRAM I/O
      3. 4.2.3 Hello World with Code Execution from OSPI PSRAM
    3. 4.3 Integrating OSPI PSRAM into Custom Applications
  8. 5Performance Analysis and Benchmarks
    1. 5.1 Read and Write Throughput
    2. 5.2 Simulated Application Benchmarks
      1. 5.2.1 XIP Benchmark
      2. 5.2.2 On-Chip Memory Benchmark
    3. 5.3 PROFINET Benchmarks
      1. 5.3.1 Performance Degradation using Fast Startup Time
      2. 5.3.2 Performance Degradation using CPU Load
  9. 6Summary
  10. 7References
  11. 8Revision History

2.2 APS6408L PSRAM Device

The APS6408L-OBMx is a volatile memory from AP Memory that supports octal DDR with a maximum frequency of 200MHz. The APS6408L-OBMx has a memory size of 8MB and supports 1KB linear burst wraps for read and write operations.

Because XIP from the external memory devices with the current AM64x OSPI controller cannot be performed in PHY mode, Tap mode is used for code execution from OSPI PSRAM.

In Tap mode, the AM64x device supports a maximum output OSPI clock frequency of 25MHz for DDR operations and 50MHz for SDR operations.

This means that the OSPI PSRAM is operating at an output OSPI clock frequency of 25MHz with octal DDR. Since DQS (Data Strobe) is not being used, the OSPI PSRAM is set to fixed-latency mode, accounting for any automatic self-refresh collisions that can occur when trying to read the data from the OSPI PSRAM.

Because the OSPI PSRAM and OSPI NOR Flash share the same OSPI controller, the memory-mapped region starting at 0x60000000 is the same for both devices. Hence, a high-speed switch is implemented to prevent bus contention and accidental overwrites of either memory device's contents.