To get good jitter results, the loop filter RC components value cannot be chosen randomly. While calculation in theory requires fluent mathematical techniques, to try different RC value combinations on the real board takes more time and provides only limited indication. To aid the loop filter design, TI's PLLatinum™ Sim is a simulation software which simplifies the calculation process and only requires a few specification details. Figure 3-1 shows the user interface and some of the parameters.

When the integral feedback divisor is used, the 2^nd-order filter can provide jitter result as good as 119fs. Further decreasing the C1 in the simulation results in lower RMS jitter. However, there is a note in the "LMX2581 Phase Noise Tips". This device has a minimum high order capacitance. What this means is that if the capacitor closest to the VCO is too small, there can be phase noise degradation in the 200kHz to 1MHz range. If this value is 3.3nF or larger, there is no degradation. If the value is 1.5nF, the degradation can be a few dB. Using a value less than 3.3nF can make sense if this requirement restricts the loop bandwidth, but using a value less than 1.5nF is not recommended.

This VCO phase noise degradation is mentioned in the External Loop Filter section of the datasheet as well, but not included in the simulation by "Use Metrics".

Change the Filter Order to 3^rd Order and Auto Parameter Strategy to Optimize Jitter, and enter Min High Order Cap as 1500pF so that the VCO phase noise is not obviously degraded. Click "Calculate Loop Filter". The GUI calculates in backend and refreshes with the suggested results as shown in Figure 3-2.