SDLS975A April   2024  – September 2025 LSF0002

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics (Translating Down): BN = 3.3V
    7. 5.7 Switching Characteristics (Translating Down): BN = 2.5V
    8. 5.8 Switching Characteristics (Translating Up): BN = 3.3V
    9. 5.9 Switching Characteristics (Translating Up):BN = 2.5V
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Auto Bidirectional Voltage Translation
      2. 7.3.2 VBIAS/ Enable
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Open-Drain Interface (I2C, PMBus, SMBus, and GPIO)
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Enable and Disable Guidelines
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Bidirectional Translation
          2. 8.2.1.2.2 Pull-Up Resistor Sizing
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Mixed-Mode Voltage Translation
      3. 8.2.3 Voltage Translation for Vref_B < Vref_A + 0.8V
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.3 Voltage Translation for Vref_B < Vref_A + 0.8V

As described in the Enable and Disable Guidelines section, it is generally recommended that VEXT,B> VEXT,A + 0.8V; however, the device can still operate in the condition where VEXT,B < VEXT,A + 0.8V as long as additional considerations are made for the design.

Typical Operation (VEXT,B > VEXT,A + 0.8V): in this scenario, pullup resistors are not required on the A-side for proper down-translation. When down translating from B to A, the A-side I/O ports will clamp at VEXT,A to provide proper voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family video.

Requirements for VEXT,B < VEXT,A + 0.8V Operation: in this scenario, there is not a large enough voltage difference between VEXT,A and VEXT,B so that the A side I/O ports will be clamped at VEXT,A, but rather at a voltage approximately equal to VEXT,B – 0.8V. For example, if VEXT,B = 1.8V and VEXT,A = 1.2V, the A-side I/Os will clamp to a voltage around 1.0V. Therefore, to operate in such a condition, the following additional design considerations must be met:

  • VEXT,B must be greater than VEXT,A during operation (VEXT,B > VEXT,A)
  • Pullup resistors should be populated on A-side I/O ports for the line to be fully pulled up to the desired voltage.

Figure 8-4 shows an example of this setup, where 1.2V ↔ 1.8V translation is achieved with the LSF0002. This type of setup also applies for other voltage nodes such as 1.8V ↔ 2.5V, 1.05V ↔ 1.5V, and others as long as the Recommended Operating Conditions table is followed.

LSF0002 1.2V to 1.8V Level Translation with LSF0002Figure 8-4 1.2V to 1.8V Level Translation with LSF0002