SFFS568B december   2022  – july 2023 DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC813R-Q1 , DP83TC813S-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for DP83TC813x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
Fault in MDI transmitter causing IEEE spec compliance issues.8
Fault in MDI transmitter causing high RF emissions.4
Fault in MDI receiver causing poor-link quality/link-loss.8
Fault in internal power circuits causing poor link quality and higher power consumption.12
Fault in internal clock circuits causing IEEE compliance issues and poor link-quality.8
Fault in GPIO causing higher RF emissions.8
Fault in GPIO causing Rgmii/JEDEC/Datasheet spec violation.8
Fault in ESD on MDI making IEC ESD performance lower than 8 KV.4
Fault in ESD on GPIOs making CDM performance lower than 2 KV.4
Digital core has stuck or transient faults causing link-up or PCS faults.36

The FMD in Table 3-1 excludes short-circuit faults across the isolation barrier. Faults for short circuits across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:

  1. The signal isolation component is OVC III according to IEC 61800-5-1. If a safety-separated extra low voltage (SELV) or protective extra low voltage (PELV) power supply is used, pollution degree 2 / OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
  2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.