SFFS685 March   2025 CDC6C-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 VSON (DLN) Package
    2. 2.2 VSON (DLF) Package
    3. 2.3 VSON (DLR) Package
    4. 2.4 VSON (DLY) Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the CDC6C-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to VDD (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality.
B No device damage, but loss of functionality.
C No device damage, but performance degradation.
D No device damage, no impact to functionality or performance.

Figure 4-1 shows the CDC6C-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the CDC6C-Q1 data sheet.

CDC6C-Q1 Pin Diagram Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • VDD = 1.8V
  • Output frequency 25MHz
  • Pin 1 configured to either Standby (Active Low) and externally pulled high with 10kΩ resistor or OE (Active High) and externally pulled low with 10kΩ resistor
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OE / ST / NC 1 Pin 1 pulled low. The device is in standby with no output signal or only the output disabled. B
GND 2 No effect. Normal operation. D
OUT 3 The output is pulled low. No output clock. Long periods of high current flow through the output transistors can cause device damage. A
VDD 4 A power-ground short can damage the device. A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OE / ST / NC 1 Pin 1 is internally pulled high. The device is enabled. Normal operation. D
GND 2 The device is not powered. The device is not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise, device damage is plausible. A
OUT 3 The output is active but not connected to the receiving device. D
VDD 4 The device is not powered. The device is not functional. B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
OE / ST / NC 1 GND Pin 1 is pulled low. The device is in standby with no output signal or only output disabled. B
GND 2 OUT The output is pulled low. No output clock. Long periods of high current flow through the output transistors can cause device damage. A
OUT 3 VDD The output is pulled high. No output clock. Long periods of high current flow through the output transistors can cause device damage. A
VDD 4 OE/ ST/ NC The device is enabled. Normal operation. D
Table 4-5 Pin FMA for Device Pins Short-Circuited to VDD
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
OE / ST / NC 1 The device is enabled. Normal operation. D
GND 2 The device is not powered. The device is not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise, device damage is plausible. A
OUT 3 The output is pulled high. No output clock. Long periods of high current flow through the output transistors can cause device damage. A
VDD 4 No effect. Normal operation. D