SFFSAD5 July 2025 TPS7B87-Q1
4.1 TO-252 Package
Figure 4-1 shows the TPS7B87-Q1 pin diagram for the TO-252 package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPS7B87-Q1 data sheet.
Figure 4-1 Pin Diagram (TO-252 Package)Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | Power is not supplied to the device. System performance depends on upstream current limiting. | B |
| PG | 2 | Power-good never asserts when the output voltage is at target, thus, potentially effecting power sequencing. | B |
| GND | 3 | No effect. Normal operation. | D |
| DELAY | 4 | Ground current is permanently increased. | C |
| OUT | 5 | Regulation is not possible; the device operates at current limit. The device can cycle in and out of thermal shutdown. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | Power is not supplied to the device, resulting in no output voltage. | B |
| PG | 2 | The power-good signal is not accessible. Power sequencing can be effected. | B |
| GND | 3 | There is no current loop for the supply voltage. The device is not operational and does not regulate. | B |
| DELAY | 4 | The power-good delay is set to the minimum delay time, t(DLY_FIX). | C |
| OUT | 5 | The device output is disconnected from the load. | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| IN | 1 | 2 - PG | Power-good functionality cannot operate correctly. PG can be damaged if the absolute maximum rating (20V) is violated. | A |
| B | ||||
| PG | 2 | 3 - GND | Power-good never asserts when the output voltage is at target, thus, potentially effecting power sequencing. | B |
| GND | 3 | 4 - DELAY | Ground current is permanently increased. | C |
| DELAY | 4 | 5 - OUT | PG can incorrectly assert when the output voltage is not at target. The pin absolute maximum rating (6V max) can be exceeded and the pin can be damaged. | A |
| B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
VIN
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| IN | 1 | No effect. Normal operation. | D |
| PG | 2 | Power-good functionality cannot operate correctly. PG can be damaged if the absolute maximum rating (20V) is violated. | A |
| B | |||
| GND | 3 | Power is not supplied to the device. System performance depends on upstream current limiting. | B |
| DELAY | 4 | PG can incorrectly assert when the output voltage is not at target. The pin absolute maximum rating (6V max) can be exceeded and the pin can be damaged. | A |
| B | |||
| OUT | 5 | Output held at VIN, regulation is not possible. Damage is possible if the absolute maximum rating is exceeded (20V max). | A |
| B |