SFFSAD6A April 2025 – September 2025 TPSM33606-Q1 , TPSM33610-Q1 , TPSM33620-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPSM336xx-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPSM336xx-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPSM336xx-Q1 data sheets.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- The product data sheet application circuit is followed.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | When not in use, this pin can be left grounded (PGOOD is not a valid signal and VOUT is normal). | D |
| EN/UVLO | 2 | VOUT = 0V; part is disabled. | B |
| VIN | 3 | VOUT = 0V. | B |
| VOUT | 4 | Goes into hiccup; short-circuit operation. | B |
| SW | 5 | Device damage. | A |
| 6 | |||
| BOOT | 7 | VOUT = 0V, the high-side FET does not turn on. | B |
| VCC | 8 | Internal circuits are disabled. No output voltage is generated. | B |
| FB | 9 | Goes into hiccup; short-circuit operation, VOUT = 0V (for fixed output), switches at maximum duty cycle (for adjustable output). Possible damage to customer load, output stage components, or both can occur. | B |
| GND | 10 | VOUT normal. | D |
| MODE/SYNC | 11 | Device runs in AUTO mode. Normal operation. | D |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | When not in use, this pin can be left open (PGOOD is not a valid signal and VOUT is normal). | D |
| EN/UVLO | 2 | Pin cannot be left floating. | B |
| VIN | 3 | VOUT = 0V. | B |
| VOUT | 4 | Loss of output voltage. | B |
| SW | 5 | Normal operation. | D |
| 6 | |||
| BOOT | 7 | Normal operation. | D |
| VCC | 8 | VCC output is unstable, can increase above 5.5V. | A |
| FB | 9 | Switches at maximum duty cycle and VOUT approaches VIN. Damage to customer load and output stage components are possible. No effect on device. | B |
| GND | 10 | VOUT can be abnormal, as reference voltage is not fixed. | B |
| MODE/SYNC | 11 | The part can go back and forth between FPWM and PFM. | C |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| MODE/SYNC | 11 | PGOOD | If PGOOD is high and < 5.5V, device runs in FPWM mode. If PGOOD is low, device runs in AUTO mode. MODE/SYNC absolute maximum is 5.5V. | A |
| PGOOD | 1 | EN/UVLO | If EN > 20V, devices connected to the PGOOD pin are damaged. | A |
| EN/UVLO | 2 | VIN | VOUT normal. | D |
| VIN | 3 | SW | Damage to the low-side FET. | A |
| SW | 5 | BOOT | VOUT = 0V, the high-side does not turn on, no CBOOT. | B |
| 6 | ||||
| BOOT | 7 | VCC | Damage occurs, breaks the VCC pin. | A |
| VCC | 8 | FB | Can be nonfunctional, no damage occurs. | B |
| FB | 9 | GND | Goes into hiccup; short-circuit operation, VOUT = 0V (for fixed output), switches at maximum duty cycle (for adjustable output). | B |
| GND | 10 | MODE/SYNC | Device runs in AUTO mode. Normal operation. | D |
| VOUT | 4 | SW | Damage occurs. | A |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | If VIN > 20V, damage to PGOOD occurs. | A |
| EN/UVLO | 2 | VOUT normal. | D |
| VIN | 3 | VOUT normal. | D |
| VOUT | 4 | Damage occurs if VIN > 16V. Customer load is damaged. | A |
| SW | 5 | Damage to the low-side FET. | A |
| 6 | |||
| BOOT | 7 | Damage occurs and BOOT ESD clamp is damaged. | A |
| VCC | 8 | If VIN > 5.5V, damage occurs. | A |
| FB | 9 | Damage occurs if VIN > 16V. | A |
| GND | 10 | VOUT = 0V. | B |
| MODE/SYNC | 11 | If VIN > 5.5V, damage occurs. | A |