SFFSAJ7 June 2025 INA187-Q1 , INA299-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the INA187-Q1 and INA299-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to Vs (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the INA187-Q1 and INA299-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA187-Q1 and INA299-Q1 data sheets.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- TA = -40°C to +125°C
- Vs = 5V
- VIN+ = 48V
- VREF = Vs+ / 2
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output is pulled down to GND and output current is short-circuit limited. When left in this configuration for a long time, under high supplies, self-heating can cause the die junction temperature to exceed 150°C. | B |
| GND | 2 | Normal operation. | D |
| IN+ | 3 | In a high-side configuration, a short from the bus supply to GND occurs. | B |
| IN- | 4 | In a high-side configuration, a short from the bus supply to GND occurs (through RSHUNT). High current flows from the bus supply to GND. The shunt can be damaged. In a low-side configuration, normal operation. | B for high-side |
| D for low-side | |||
| REF | 5 | Normal operation if the REF pin is at GND potential by design; otherwise, the system measurement is incorrect. | D if REF = GND by design |
| C otherwise | |||
| VS | 6 | Power supply shorted to GND. | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output can be left open. There is no effect on the device, but the output is not measured. | C |
| GND | 2 | No power to the device. The device can be biased through inputs. Output is no longer referenced to GND. | B |
| IN+ | 3 | The shunt resistor is not connected to the amplifier. The IN+ pin can float to an unknown value. Output goes to an unknown value, not to exceed Vs or GND. | B |
| IN- | 4 | The shunt resistor is not connected to the amplifier. The IN- pin can float to an unknown value. Output goes to an unknown value, not to exceed Vs or GND. | B |
| REF | 5 | Output common-mode voltage is not defined. Output does not maintain a linear relationship with differential input voltage. | C |
| VS | 6 | No power to device. Device can be biased through inputs. Output is incorrect and close to GND. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| OUT | 1 | 2 - GND | Output is pulled down to GND and output current is short-circuit limited. When left in this configuration for a long time, under high supplies, self-heating can cause the die junction temperature to exceed 150°C. | B |
| GND | 2 | 3 - IN+ | Power supply is shorted to GND. | B |
| IN+ | 3 | 4 - IN- | Inputs are shorted together, so no sense voltage is applied. Output stays close to REF potential. | B |
| IN- | 4 | 5 - REF | In a high-side configuration, REF is shorted to the bus supply (through Rshunt). High current flows from the bus supply to GND, shunt can be damaged. In a low-side configuration, normal operation (if REF is at GND potential by design) | B for high-side |
| C for low-side | ||||
| D if REF = GND by design | ||||
| REF | 5 | 6 - VS | Normal operation if the REF pin is at Vs potential by design; otherwise, the system measurement is incorrect. | D if REF=Vs by design |
| C otherwise | ||||
| VS | 6 | 1 - OUT | Output is pulled to Vs and the output current is short-circuit limited. When left in this configuration for a long time, under high supplies, self-heating can cause the die junction temperature to exceed 150°C. | B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to Vs
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output is pulled to Vs and the output current is short-circuit limited. When left in this configuration for a long time, under high supplies, self-heating can cause the die junction temperature to exceed 150°C. | B |
| GND | 2 | Power supply is shorted to GND. | B |
| IN+ | 3 | In a high-side configuration, the device power supply is shorted to the bus supply (through RSHUNT). In a low-side configuration, the device power supply is shorted to GND. | B |
| IN- | 4 | In a high-side configuration, the device power supply is shorted to the bus supply. In a low-side configuration, the device power supply is shorted to GND (through RSHUNT). | B |
| REF | 5 | Normal operation if the REF pin is at Vs potential by design; otherwise, the system measurement is incorrect. | D if REF=Vs by design |
| C otherwise | |||
| VS | 6 | Normal operation. | D |