SFFSB63 September 2026 TPS1HC120-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a
failure mode analysis (FMA) for the pins of the TPS1HC120-Q1. The
failure modes covered in this document include the typical pin-by-pin failure scenarios:
Figure 4-1 Pin Diagram (8-Pin SOT (Top View), C
Version)Following are the assumptions of use and the device configuration assumed for the pin
FMA in this
section:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-1 TI Classification of Failure
Effects
Figure 4-1 shows the TPS1HC120-Q1 pin diagram. For a detailed description
of the device pins, see the Pin Configuration and Functions section in the TPS1HC120-Q1 datasheet.| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 Pin Diagram (8-Pin SOT (Top View), C
Version)- The device pins are connected per the recommendation in the datasheet, including pullup and pulldown resistors, as needed.
- The datasheet recommendations for operating conditions, external component selection, and PCB layout are followed.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FLT1 | 1 | The reported current limit, short circuit, or thermal shutdown status is potentially erroneous. | B |
| ILIM | 2 | The current limit is set at 2.1A typical, as per the datasheet. | C |
| EN_AUX | 3 | No effect if EN is not also shorted to ground. | D |
| EN | 4 | The FET is turned off. | B |
| FLT2 | 5 | The reported ON state open load fault status is potentially erroneous. | B |
| GND | 6 | Any GND network, connected for protection, is bypassed. | B |
| VOUT | 7 | The current limit of the device engages, and thermal protection turns off the FET. | B |
| VBB | 8 | The output stages are not powered, and the FET does not turn ON. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FLT1 | 1 | Current limit, short circuit, or thermal shutdown condition is not reported. | B |
| ILIM | 2 | Current limit is set at 2.1A as per datasheet. | C |
| EN_AUX | 3 | No effect if EN1 is also not open circuited. | D |
| EN | 4 | The FET is turned off. | B |
| FLT2 | 5 | ON state open load fault is not reported. | B |
| GND | 6 | The loss of ground detection engages, and the device turns OFF. | B |
| VOUT | 7 | During the ON state of the device, output is disconnected. | B |
| VBB | 8 | The device is not powered. | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| FLT1 | 1 | 2 (ILIM) | Current limit and fault response are not predictable. | B |
| ILIM | 2 | 3 (EN_AUX) | Current limit value is not predictable. | B |
| EN_AUX | 3 | 4 (EN) | No effect. | D |
| FLT2 | 5 | 6 (GND) | The reported ON state open load fault status is potentially erroneous. | B |
| GND | 6 | 7 (VOUT) | The current limit of the device engages, and thermal protection turns off the FET. | B |
| VOUT | 7 | 8 (VBB) | The output is pulled to the supply voltage. | B |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FLT1 | 1 | If pin voltage exceeds the absolute maximum rating, device damage is possible due to voltage breakdown on the ESD circuit. | A |
| ILIM | 2 | If pin voltage exceeds the absolute maximum rating, device damage is possible due to voltage breakdown on the ESD circuit. | A |
| EN_AUX | 3 | If pin voltage exceeds the absolute maximum rating, device damage is possible due to voltage breakdown on the ESD circuit. | A |
| EN | 4 | If pin voltage exceeds the absolute maximum rating, device damage is possible due to voltage breakdown on the ESD circuit. | A |
| FLT2 | 5 | If pin voltage exceeds the absolute maximum rating, device damage is possible due to voltage breakdown on the ESD circuit. | A |
| GND | 6 | The supply power is bypassed, and the device stays OFF. | B |
| VOUT | 7 | The output is pulled to the supply voltage. | B |
| VBB | 8 | No effect. | D |