SFFSBC8 October 2026 TLV9023L-Q1
4.1.1 WQFN (16)
Figure 4-1 shows the pin diagram for the WQFN. For a detailed description of the device pins, see the Pin Configuration and Functions section in the datasheet.
Figure 4-1 Pin
DiagramTable 4-2 Pin FMA for Device Pins
Short-Circuited to Negative Supply (V-) Pin
| Pin Analysis for Pin Short-Circuit to Negative Supply (V-) | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Effected | Description of Potential Failure Effects | Comments | Failure Effect Class |
| CLR | 1 | No | Yes | Latched outputs cannot be cleared | B |
| OUT3 | 2 | No | Yes | Output held low independent of differential input voltage | B |
| OUT2 | 3 | No | Yes | Output held low independent of differential input voltage | B |
| OUT1 | 4 | No | Yes | Output held low independent of differential input voltage | B |
| AND_OUT | 5 | Potential | Yes | Thermal stress due to high power dissipation if AND_OUT goes high | A |
| N/C | 6 | No | No | Not effected | D |
| V+ | 7 | No | Yes | Main supply shorted out (no power to device) | B |
| N/C | 8 | No | No | Not effected | D |
| IN1+ | 9 | No | Yes | OUT1 goes low, if other input is positive | B |
| IN1- | 10 | No | Yes | OUT1 goes high, if other input is positive | B |
| IN2+ | 11 | No | Yes | OUT2 goes low, if other input is positive | B |
| IN2- | 12 | No | Yes | OUT2 goes high, if other input is positive | B |
| IN3+ | 13 | No | Yes | OUT3 goes low, if other input is positive | B |
| IN3- | 14 | No | Yes | OUT3 goes high, if other input is positive | B |
| V- | 15 | No | No | No change if same node as (V-) | D |
| AND_IN | 16 | No | Yes | AND_OUT goes low | B |
Table 4-3 Pin FMA for Device Pins
Short-Circuited to Positive Supply (V+) Pin
| Pin Analysis for Pin Short-Circuit to Positive Supply (V+) | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Effected |
Description of Potential Failure Effects | Comments | Failure Effect Class |
| CLR | 1 | No | Yes | Latched outputs cannot be cleared | B |
| OUT3 | 2 | Potential | Yes | Thermal stress due to high power dissipation if OUT3 goes low | A |
| OUT2 | 3 | Potential | Yes | Thermal stress due to high power dissipation if OUT2 goes low | A |
| OUT1 | 4 | Potential | Yes | Thermal stress due to high power dissipation if OUT1 goes low | A |
| AND_OUT | 5 | Potential | Yes | Thermal stress due to high power dissipation if AND_OUT goes low | A |
| N/C | 6 | No | No | Not effected | D |
| V+ | 7 | No | Yes | No change if same node as (V+) | D |
| N/C | 8 | No | No | Not effected | D |
| IN1+ | 9 | No | Yes | OUT1 goes high, if other input is less than (V+) | B |
| IN1- | 10 | No | Yes | OUT1 goes low, if other input is less than (V+) | B |
| IN2+ | 11 | No | Yes | OUT2 goes high, if other input is less than (V+) | B |
| IN2- | 12 | No | Yes | OUT2 goes low, if other input is less than (V+) | B |
| IN3+ | 13 | No | Yes | OUT3 goes high, if other input is less than (V+) | B |
| IN3- | 14 | No | Yes | OUT3 goes low, if other input is less than (V+) | B |
| V- | 15 | No | Yes | Main supply shorted out (no power to device) | B |
| AND_IN | 16 | No | Yes | AND_OUT goes high, if other inputs are positive | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Analysis for Pin Short-Circuit to Negative Supply (V-) | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Effected |
Description of Potential Failure Effects | Comments | Failure Effect Class |
| CLR to OUT3 | 1 | No | Yes | Outputs can clear if OUT3 transitions from high to low | B |
| OUT3 to OUT2 | 2 | No | Yes | Outputs go low if either output goes low | B |
| OUT2 to OUT1 | 3 | No | Yes | Outputs go low if either output goes low | B |
| OUT1 to AND_OUT | 4 | Potential | Yes | Thermal stress due to high power dissipation if OUT1 goes low and AND_OUT goes high | A |
| AND_OUT to N/C | 5 | Yes | Yes | Not effected | D |
| N/C to V+ | 6 | No | Yes | Not effected | D |
| V+ to N/C | 7 | No | Yes | Not effected | D |
| N/C to IN+ | 8 | No | No | Not effected | D |
| IN1+ to IN1- | 9 | No | Yes | OUT1 can go high or low | B |
| IN1- to IN2+ | 10 | No | Yes | OUT1 and OUT2 can go high or low | B |
| IN2+ to IN2- | 11 | No | Yes | OUT2 can go high or low | B |
| IN2- to IN3+ | 12 | No | Yes | OUT2 and OUT3 can go high or low | B |
| IN3+ to IN3- | 13 | No | Yes | OUT3 can go high or low | B |
| IN3- to V- | 14 | No | Yes | OUT3 goes high, if other input is positive | B |
| V- to AND_IN | 15 | No | No | AND_OUT goes low | B |
| AND_IN to CLR | 16 | No | Yes | AND_OUT can be high or low and outputs can be cleared if AND_IN transitions from high to low | B |
Table 4-5 Pin FMA for Device Pins Open-Circuited
| Pin Analysis for Device Pins Open-Circuited | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Effected |
Description of Potential Failure Effects | Comments | Failure Effect Class |
| CLR | 1 | No | Yes | Latched outputs cannot be cleared | B |
| OUT3 | 2 | No | Yes | OUT3 held high by external pullup resistor independent of differential input voltage | B |
| OUT2 | 3 | No | Yes | OUT2 held high by external pullup resistor independent of differential input voltage | B |
| OUT1 | 4 | No | Yes | OUT1 held high by external pullup resistor independent of differential input voltage | B |
| AND_OUT | 5 | No | Yes | AND_OUT function not available | B |
| N/C | 6 | No | Yes | Not effected | D |
| V+ | 7 | No | Yes | Main supply not powered | B |
| N/C | 8 | No | No | Not effected | D |
| IN1+ | 9 | No | Yes | OUT1 can be high or low | B |
| IN1- | 10 | No | Yes | OUT1 can be high or low | B |
| IN2+ | 11 | No | Yes | OUT2 can be high or low | B |
| IN2- | 12 | No | Yes | OUT2 can be high or low | B |
| IN3+ | 13 | No | Yes | OUT3 can be high or low | B |
| IN3- | 14 | No | Yes | OUT3 can be high or low | B |
| V- | 15 | No | No | Main supply not powered | D |
| AND_IN | 16 | No | Yes | AND_OUT goes high, if other inputs are positive | B |