SLAA380B December   2007  – September 2018 MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

 

  1.   Migrating From MSP430F16x MCUs to MSP430F261x MCUs
    1.     Trademarks
    2. 1 Comparison of MSP430F1xx and MSP430F2xx Families
    3. 2 Hardware Considerations for MSP430F16x to MSP430F261x Migration
      1. 2.1 Device Package and Pinout
      2. 2.2 Current Consumption
      3. 2.3 Operating Frequency and Supply Voltage
      4. 2.4 Device Errata
    4. 3 MSP430F16x to MSP430F261x Migration – Firmware Considerations
      1. 3.1 CPU and Memory Considerations
        1. 3.1.1 Extended Memory Architecture
        2. 3.1.2 Subroutine Parameter Passing and Stack Frame
        3. 3.1.3 MSP430X Instruction Cycle Count Optimizations
        4. 3.1.4 Device Memory Map
        5. 3.1.5 Information Flash Memory
      2. 3.2 Serial Communication – USART Versus USCI
        1. 3.2.1 UART Mode
        2. 3.2.2 SPI Mode
        3. 3.2.3 I2C Mode
      3. 3.3 Clock System
        1. 3.3.1 LFXT1 and XT2 Oscillators
        2. 3.3.2 Digitally Controlled Oscillator (DCO)
      4. 3.4 Bootloader
      5. 3.5 Interrupt Vectors
      6. 3.6 Beware of Reserved Bits!
      7. 3.7 Timers
      8. 3.8 Analog Comparator
    5. 4 References
  2.   Revision History

3.8 Analog Comparator

On the Comparator_A of MSP430F16x devices, disabling the digital port functionality for an I/O pin by setting the associated bit in the Port Disable Register CAPD to prevent parasitic cross currents during analog measurements disables the digital CMOS input buffer. However, on MSP430F261x devices with Comparator_A+, setting a CAPDx bit disables both input and output buffer for that pin.