SLAAE45 September   2021 TMUXHS4412

 

  1.   Trademarks
  2. 1Introduction
  3. 2Practical PCB Design Rules
    1. 2.1 PCIe® Specific Standard
    2. 2.2 PCIe® High-Speed Signal Layout Guidelines
    3. 2.3 Vias, Stub, and ESD/EMI Layout Guidelines
    4. 2.4 Power and Grounding Layout Guidelines
  4. 3Layout Examples
  5. 4Summary
  6. 5References

2.4 Power and Grounding Layout Guidelines

  1. Use a complete ground plane and a complete power plane to avoid noise coupling. But in most cases, split ground planes cannot be avoided. If split ground planes are essential:
    • Do not route signals over a gap. Always strive for the return current flow with the smallest loop area.
    • Connect split ground planes only at one point. More common-ground connections can create ground loops, and this increases radiation.
    • Power planes should only reference their own ground plane. They should not overlap with another ground plane.
    • Do not connect bypass capacitors between a power plane and an unrelated ground plane. Again, noise can be coupled from one supply system into the other.
  2. Separate digital and analog power supplies with filtering and bypassing.
  3. Put the largest-value filter capacitors near a power connector and supply inputs.
  4. Place high-quality X7R decoupling capacitors close to device pins.
    • Use multiple capacitors (0.1 μF, 0.01 μF, and 1 μF) in parallel to offer low impedance over higher frequency ranges.
    • Place the smallest-value capacitors closest to the power pin.
    • Connect the pad of the capacitor directly to a via to the ground plane. Use two or three vias to get a low-impedance connection to ground.
    • Keep the traces from decoupling caps to ground as short and wide as possible
GUID-B200CE30-0989-4CEC-B30E-B5578F28CE46-low.gif Figure 2-6 Poor and Good Placement and Routing of Bypass Capacitors