SLAAE57 June 2022 TAS2563
The TAS2563 provides one PDM input. Figure 1-4 illustrates the double data rate nature of the PDM input. It has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of the clock.
The PDM inputs are sampled by the PDMCLK pin, which can be configured as either a PDM clock input or a PDM clock output. The PDM_MIC_EDGE and PDM_MIC_SLV register bits select the sample clock edge and output or input mode PDM clock signal. In output mode the PDMCLK pin can disable the clocks (and drive logic 0) by setting the PDM_GATE_PAD0 register bit low. When configured as a clock input, the PDM clock input does not require a specific phase relationship to the system clock (SBCLK in TDM | I2S Mode), but must be from the same source as the audio sample rate. This is equivalent to 64 | 32 |16 (about 3 MHz) or 128 | 64 | 32 (about 6 MHz) times a single | double | quadruple speed sample rate. The PDM rate is set by the PDM_RATE_PAD0. When PDMCLK pin is configured as a clock output, the TAS2563 outputs a 50% duty cycle clock of frequency that is set by the PDM_RATE_PAD0 and register bit (64 | 32 | 16 or 128 | 64 | 32 times a single | double | quadruple speed sample rate).
The data from the PDM microphone will have digital gain up to 30 dB. The two microphones can have independent gains.