SLAAE76B march   2023  – june 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0G Hardware Design Check List
  5. 2 Power Supplies in MSPM0G Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  7. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Oscillators
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug port pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 MCAN Design Considerations
    4. 7.4 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High-Speed GPIOs (HSIO)
    4. 8.4 High-Drive GPIOs (HDIO)
    5. 8.5 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    6. 8.6 Communicate With a 1.8-V Device Without a Level Shifter
    7. 8.7 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  14. 11References
  15. 12Revision History

7.2 UART and LIN Resources and Design Considerations

The MSPM0G series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in Table 7-4, UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function.

Table 7-4 UART Features
UART Features UART0 (Extend) UART1 (Main)
Active in Stop and Standby Mode Yes Yes
Separate transmit and receive FIFOs Yes Yes
Support hardware flow control Yes Yes
Support 9-bit configuration Yes Yes
Support LIN mode Yes -
Support DALI Yes -
Support IrDA Yes -
Support ISO7816 Smart Card Yes -
Support Manchester coding Yes -

The MSPM0G UART module can support up to 10-MHz baud date in Power Domain1 to support almost all UART applications.

Table 7-5 MSPM0G UART Specifications
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
fUART UART input clock frequency UART in Power Domain1 80 MHz
fUART UART input clock frequency UART in Power Domain0 40 MHz
fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz
fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 5 MHz
tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns
AGFSELx = 1 8 15 55 ns
AGFSELx = 2 18 38 115 ns
AGFSELx = 3 30 74 165 ns

Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness.

The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME).

The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode and wake-up from low-power mode over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. Figure 7-1 shows a typical interface implemented using the TI TLIN1021A LIN transceiver.

GUID-F95B039E-FCFA-4FB1-975B-B03DA1111EE7-low.png Figure 7-1 Typical LIN TLIN1021A Transceiver

Only a single wire is required for communication and is commonly included in the vehicle wiring harness. Figure 7-2 and Figure 7-3 show typical interfaces implemented using the TI TLIN1021A LIN transceiver, for more details refer to the TLIN1021 data sheet.

GUID-452D63EA-A263-41DC-B4BD-4D376FC759E9-low.png Figure 7-2 Typical LIN Application (Commander) With MSPM0G
GUID-F9A69F67-B989-46FA-94C9-A40E0F2F03C8-low.png Figure 7-3 Typical LIN Application (Responder) With MSPM0G