SLAAEF9 November   2023 MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Renesas RL78 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 The IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad
    2. 2.2 Migration Process
      1. 2.2.1 Step 1. Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3. Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4. Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Flash Memory Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
        3. 3.2.2.3 Flash Memory Registers of RL78
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power UP and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
        1. 3.4.1.1 MSPM0 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of RL78
        2. 3.6.1.2 Interrupt Management of MSPM0
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Link Controller (ELC) of RL78
      4. 3.6.4 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming of MSPM0
        2. 3.7.2.2 Serial Programming (Using External Device) of RL78
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Inter-Integrated Circuit (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)

3.4.2 Clock Signal Comparison

Different clock signals can be divided to source other clocks and be distributed across the multitude of peripherals.

Table 3-8 Clock Signal Comparison
Clock Description RL78 Clock MSPM0 Clock
External digital clock input High frequency EXCLK (fEX) HFCLK_IN
Low frequency EXCLKS (fEXS) LFCLK_IN
High-frequency external clock fMX HFCLK
Low-frequency external clock fSUB (1) Selection of LFCLK_IN and LFXT
PLL circuit output clock fPLL SYSPLLCLK0, SYSPLLCLK1,
SYSPLLCLK2x (2)
Main system clock fMAIN (3) MCLK, ULPCLK (4) (BUSCLK)
High-frequency clock for CPU/peripherals fMAIN or fMP/n (5) Selection of HSCLK (6) and SYSOSC
Low-frequency clock for CPU/peripherals fSL LFCLK (fixed 32 kHz)
Source CPU fCLK CPUCLK
Clock for most peripheral hardware fCLK MCLK, ULPCLK
Available clock for high-speed peripherals fMX, fIH, fMAIN, fPLL, fMP, fCLK MCLK
Available clock for low-speed low-power peripherals fSUB,fIL, fSL, fCLK ULPCLK
Fixed frequency clock N/A MFCLK: 4 MHz, synchronized to MCLK
MFPCLK: 4 MHz
(1) fSUB is the subsystem clock which can be sourced from low-frequency external oscillator (fXT) or the low-frequency external digital clock input (EXCLKS).
(2) SYSPLLCLK2x is twice the speed of the output of the PLL and can be divided down.
(3) The main system clock of RL78 is sourced from fMX or fHOCO/fIH.
(4) The main system clock of MSPM0 is sourced from LFCLK, HSCLK, or SYSOSC. The MCLK is the main system clock for PD1 and the ULPCLK, derived from MCLK, is the main system clock for PD0.
(5) The fMP is the main system/PLL selection clock, and n can be selected as 1, 2, 4…… Most RL78 devices select fMAIN as the high-frequency clock for CPU/peripherals, and some RL78 devices select fMP/n as the high-frequency clock for CPU/peripherals.
(6) The HSCLK is sourced from SYSPLL or HFCLK.
Table 3-9 Peripheral Clock Sources
Peripheral RL78 MSPM0
Real-time clock (RTC) fIH, fIL, fMX, fSUB, fCLK LFCLK (LFOSC, LFXT)
UART fCLK BUSCLK, MFCLK, LFCLK
SPI/CSI (simplified SPI) fCLK BUSCLK, MFCLK, LFCLK
I2C fCLK BUSCLK, MFCLK
CAN fMX, fMP, fCLK PLLCLK1, HFCLK
ADC fCLK ULPCLK, HFCLK, SYSOSC
TIMERS fHOCO, fIL, fMX, fSL, fPLL, fMP, fCLK, fTMKB2 (1) BUSCLK, MFCLK, LFCLK
COMPARATOR fPLL, fCLK ULPCLK
(1) fTMKB2 clock is only used to source the 16-bit timers of RL78 MCU.