SLAAEK4 January   2024 MSPM0C1104

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Comparison Between TIMA and TIMG
  6. 3 Use Case - 3 Pairs of Complementary PWM with Deadband Insertion
    1. 3.1 Principle
    2. 3.2 Implement
  7. 4 Use Case - Timing-Critical PWM Control with Shadow Load and Compare
    1. 4.1 Principle
    2. 4.2 Implement
  8. 5 Use Case - Fault Handler
    1. 5.1 Principle
    2. 5.2 Implement
  9. 6 Use Case – PWM Disable with Software Force Output
    1. 6.1 Principle
    2. 6.2 Implement
  10. 7 Use Case - Asymmetric PWM
    1. 7.1 Principle
    2. 7.2 Implement
  11. 8 Use Case – Optimal Interrupt Generation with Repeat Counter
    1. 8.1 Principle
    2. 8.2 Implement
  12. 9 Summary
  13. 10References

6.1 Principle

In addition to the fault handler, users can also force the PWM output in software. Each output channel signal can be forced to a high or low level directly by software, independently of any comparison between the compare register and the counter.

The following is the key feature for the use case. All timer modules support the feature.

  • Generate center-aligned or edge-aligned PWMs
  • Set the SWFRCACT bit in the TIMx.CCACT_xy[0/1] register