SLAAEK4 January   2024 MSPM0C1104 , MSPM0C1105 , MSPM0C1106 , MSPM0H3216

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Comparison Between TIMA and TIMG
  6. 3 Use Case - 3 Pairs of Complementary PWM with Deadband Insertion
    1. 3.1 Principle
    2. 3.2 Implement
  7. 4 Use Case - Timing-Critical PWM Control with Shadow Load and Compare
    1. 4.1 Principle
    2. 4.2 Implement
  8. 5 Use Case - Fault Handler
    1. 5.1 Principle
    2. 5.2 Implement
  9. 6 Use Case – PWM Disable with Software Force Output
    1. 6.1 Principle
    2. 6.2 Implement
  10. 7 Use Case - Asymmetric PWM
    1. 7.1 Principle
    2. 7.2 Implement
  11. 8 Use Case – Optimal Interrupt Generation with Repeat Counter
    1. 8.1 Principle
    2. 8.2 Implement
  12. 9 Summary
  13. 10References

4.1 Principle

For MSPM0, some timer modules have a shadow load and shadow compare register feature which gives the user the flexibility of holding the update of load and CC values until a certain event occurs. This is useful in timing-critical applications where PWM control signals need to be updated with correct timings, such as duty cycle updates.

To control PWM with shadow load / compare, TIMA or specific TIMG are required. The following is the key feature for the use case.
  • Generate center-aligned / edge-aligned PWMs
  • Enable shadow load
  • Configure CC update method