SLAAEM7 September   2024 TAS2120 , TAS2320

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Application Schematics
    1. 2.1 Recommended Component Ratings
    2. 2.2 Reference Schematic
  6. 3Design Guidelines
    1. 3.1  VDD Pin
    2. 3.2  PVDD Pin
    3. 3.3  GREG Pin
    4. 3.4  SW Pin
    5. 3.5  VBAT Pin
    6. 3.6  OUT_P and OUT_N Pins
      1. 3.6.1 Optional EMI Filter on Output
    7. 3.7  IOVDD Pin
    8. 3.8  DREG Pin
    9. 3.9  Digital I/O Pins
    10. 3.10 Ground Pins
    11. 3.11 HW Selection Pins
  7. 4EMI Specific Guidelines
  8. 5Summary
  9. 6References

5 Summary

Table 5-1 summarizes the recommended design and layout practices for the different pins of the device.

Table 5-1 Summarized Design and Layout Guidelines
SectionPin or SectionMaximum Parasitic Trace Inductance (pH)Recommended Guidelines
1VDD650Decouple with a capacitor ≥ 2.2µF, placed as close to device as possible
2PVDD

600

Decouple with capacitor 3 x 10µF or 2 x 22µF, placed as close as possible to device
Needs small package 0.1µF capacitor (0201) placed closest to the device, with minimal ESL
Account for derating due to PVDD voltage
Wide traces with high current carrying capability
3GREG4000Decouple with 0.1μF capacitor to PVDD pin
Connect directly to PVDD pin with star connection
4SWPlace inductor as close as possible to device
Wide traces to carry high current and minimize parasitic resistance critical for efficiency (reduced I2R losses)
Decouple with ≥ 10µF capacitor near inductor
Minimize parasitic capacitance to ground to reduce switching losses
Leave pin unconnected in external PVDD mode
5VBAT950Connect directly to power source using star connection
Decouple with ≥ 1µF capacitor, placed as close as possible to device
5VBAT_SNSConnect directly to power source using star connection
Optional connection in VBAT1S mode, connect to ground if unused
6OUT_P / OUT_NDecouple with ≥ 1µF capacitor, placed as close as possible to device
Wide traces capable of carrying high current
Minimize parasitic capacitance to ground to reduce switching losses
7IOVDDCan be shorted to VDD near the device pin if 1.8V is the required I/O supply. Recommended to use both C2 and C3 capacitors even when shorted, with the capacitors placed close to the VDD pin
8DREGDecouple with ≥ 1µF capacitor as close as possible to device
9DigitalAvoid routing near high-voltage switching nodes like SW, OUT_P, OUT_N to avoid coupling
10GroundShort BGND or PGND pins on top layer
Avoid common inductance to ground plane between PGND or BGND and GND pins
Total parasitic inductance to PCB ground critical for device performance. Use multiple vias to minimize inductance
11HW Selection PinsPlace HW setting resistors as close as possible to the IC. Parasitic capacitance after the resistor doesn't matter.