SLAAEN0 September   2024 MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Low-Frequency Subsystem Introduction
    1. 2.1 Resetting LFSS IP Using VBAT
    2. 2.2 Power Domain Supply Detection
      1. 2.2.1 Start-Up Sequences
      2. 2.2.2 LFSS IP Behavior
    3. 2.3 LFXT, LFOSC
    4. 2.4 Independent Watchdog Timer (IWDT)
    5. 2.5 Tamper I/O
      1. 2.5.1 IOMUX Mode
      2. 2.5.2 Tamper Mode
        1. 2.5.2.1 Tamper Event Detection
        2. 2.5.2.2 Timestamp Event Output
        3. 2.5.2.3 Heatbeat Generator
    6. 2.6 Scatchpad Memory (SPM)
    7. 2.7 Real-Time Clock (RTC)
    8. 2.8 VBAT Charging Mode
  6. 3Application Examples
    1. 3.1 Tamper I/O Heartbeat Example
    2. 3.2 RTC Tamper I/O Timestamp Event Example
    3. 3.3 Supercapacitor Charging Example
    4. 3.4 LFOSC Transition Back to LFXT Example
    5. 3.5 RTC_A Calibration
      1. 3.5.1 Peripheral ADC 12
      2. 3.5.2 RTC_A

2.2.1 Start-Up Sequences

When the VBAT domain is supplied first on a unpowered SoC, the LFSS IP starts with the asynchronous sequence of the VBAT PMU. The release of the VBAT POR is around 0.9V which starts the VBAT REF circuit. When the OK signal is asserted, the signal enables the BOR circuit. Once the BOR indicates the VBAT has surpassed the minimum operating supply voltage at 1.62V, the LDO-VRTC is enabled. Once the VRTC domain has reached 1.35V, the comparator indicates a good status which releases the reset from the VRTC domain. After the reset, the LFOSC starts a 32kHz clock to operate the VBAT REF and BOR circuit in sampled mode. The LFSS IP power consumption in this state is expected to be below the specification limit to provide a 10-year lifetime from a coin cell battery.

MSPM0L2228 Start-Up Sequence When VBAT Comes FirstFigure 2-2 Start-Up Sequence When VBAT Comes First

When the VDD domain is supplied first, then the SoC starts with the asynchronous sequence of the PMU. This is the same start-up sequence as the SoC without LFSS IP. The difference is the unavailability of the LFCLK for use in the SoC. The VBAT-detector indicates VBAT is not present yet. In this case, the SoC cannot go into STANDBY mode as 32kHz is required for the STANDBY mode.

MSPM0L2228 Start-Up Sequence When VDD Comes FirstFigure 2-3 Start-Up Sequence When VDD Comes First