SLAAEV2 October   2026 TAS5815

 

  1.   1
  2.   Abstract
  3. 1Introduction to Class D Amplifier Overcurrent Protection Principles
  4. 2Analysis of Common OC Issues and Solutions
    1. 2.1 Software Configuration
    2. 2.2 Hardware Configuration
  5. 3Analysis and Solutions for Fake OC Issues
  6. 4Summary
  7. 5References

Hardware Configuration

The most important aspect of hardware configuration is the selection of the inductor parameters. The inductor saturation current I_SAT must be greater than all possible peak currents in the system; otherwise, inductor saturation will cause the circuit to lose control and may even damage the device. In audio amplifier design, the following three scenarios with large instantaneous currents must be considered:

  1. At power-up, when the duty cycle rapidly increases from 0 to θ, the LC filter generates an inrush charging current:
    Equation 1. I _ p e a k _ p o w e r _ u p ≈ P V D D × √ ( C / L ) × s i n ( 1 / √ ( L × C ) × θ / F s w )
  2. Peak current during audio clipping:
    Equation 2. I _ p e a k _ c l i p p i n g ≈ P V D D × ( 1 - θ ) / ( F s w × L )
  3. During normal playback, the inductor peak current corresponding to the maximum output power:
    Equation 3. I _ p e a k _ o u t p u t _ p o w e r ≈ √ ( 2 × M a x _ O u t p u t _ P o w e r / R _ s p e a k e r _ l o a d )

    The inductor saturation current must be greater than or equal to the maximum of these three scenarios to ensure safe operation of the system under all conditions.

    Equation 4. I _ S A T ≥ M A X ( I _ p e a k _ p o w e r _ u p , I _ p e a k _ c l i p p i n g , I _ p e a k _ o u t p u t _ p o w e r )

The chip datasheet generally contains detailed requirements for inductor parameter selection. Please strictly follow the datasheet when selecting components, or contact a TI FAE for design assistance.

In addition to abnormal OCP issues caused by improper inductor parameter selection, excessive noise at the SW node can also lead to abnormal current and thus abnormal OCP. Figure 2-2 shows the SW node voltage waveform under normal conditions, where CH1 is the FAULT pin waveform, CH2 is the SW node voltage waveform, and CH4 is the inductor current waveform. It can be seen that under normal operating conditions, the voltage overshoot at the SW pin is very small, and the current detected inside the chip at this time is closer to the actual inductor current.

 SW node voltage waveform under normal conditionsFigure 2-2 SW node voltage waveform under normal conditions

Figure 2-3 shows the SW node voltage waveform when the noise is excessive, where CH2/CH3 are the SW node-to-ground voltage waveforms of the left and right channels. It can be seen that excessive noise causes a large overshoot during the voltage rise period, which in turn causes the instantaneous current detected inside the chip to be excessive, thereby triggering OCP, pulling the FAULT level low, and causing the chip to report an error. A common hardware solution is to reserve an RC snubber network on the board to reduce the voltage overshoot at the SW node and mitigate the OCP issue. In addition, some devices also provide registers for adjusting the slew rate, which allows optimization from the software side as well.

 Excessive SW node noise causing current overshoot and triggering OCPFigure 2-3 Excessive SW node noise causing current overshoot and triggering OCP