3 Analysis and Solutions for Fake OC Issues

In addition to conventional OCP issues, another common category of OCP is Fake OC, or false OCP. As the name implies, the actual inductor current has not reached the overcurrent threshold, but the current detection mechanism produces an abnormally large detection result under certain special scenarios, thereby triggering the internal OC protection.

The core condition for triggering Fake OC is a low-frequency, high-amplitude input signal combined with a relatively large output impedance. The most extreme scenario is an input of a high-amplitude, low-frequency signal with the output open-circuited. In this case, the real load current is zero, yet the system's overcurrent protection is falsely triggered. The root cause of this false triggering is insufficient charging of the BST bootstrap capacitor, which causes the gate drive voltage (BST − OUT) of the high-side transistor M1 to drop abnormally, preventing M1 from fully turning on and causing Rdson to rise significantly. Since the OC detection circuit samples current based on Vsense = Iout × Rdson, the abnormal increase in Rdson makes the sampled voltage artificially high, ultimately exceeding the OC threshold and triggering false protection.

As shown in Figure 2-1, the basic principle of OC is illustrated from the internal architecture of the Class D amplifier and the MOS switching waveforms. The BST capacitor needs to be charged through the bootstrap diode during the PWM low-level period (when the low-side transistor M2 is on). Under large audio amplitude conditions, the PWM duty cycle approaches 100%, the low-level time is extremely short, and the charging time of the BST capacitor is severely insufficient. Under low audio frequency conditions, the high-duty-cycle state lasts longer, and the BST capacitor continues to discharge over an extended period without being effectively replenished, causing its voltage to keep dropping. Under high load impedance conditions, the RC time constant at the switching node increases, the PWM rising and falling edges become slower, further compressing the effective charging window of the BST capacitor. These three factors compound one another and together cause a severe drop in BST voltage.

For solutions to this type of OC issue, the most direct approach is to increase the BST capacitor value to enhance its energy storage capability and thereby delay the voltage drop. Of course, based on this cause, other approaches can also address this type of false OC issue, such as forcibly inserting a minimum low-level time inside the chip, monitoring the BST voltage in real time, or introducing temperature/voltage compensation into the OC detection to dynamically adjust the OC threshold according to the actual BST voltage.