SLASF71A December   2022  – July 2025 DAC53204W , DAC63204W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: General
    9. 5.9  Timing Requirements: I2C Standard Mode
    10. 5.10 Timing Requirements: I2C Fast Mode
    11. 5.11 Timing Requirements: I2C Fast Mode Plus
    12. 5.12 Timing Requirements: SPI Write Operation
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 5.15 Timing Requirements: GPIO
    16. 5.16 Timing Diagrams
    17. 5.17 Typical Characteristics: Voltage Output
    18. 5.18 Typical Characteristics: Current Output
    19. 5.19 Typical Characteristics: Comparator
    20. 5.20 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 External Reference
          3. 6.4.1.1.3 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Fault-Dump Mode
      5. 6.4.5 Application-Specific Modes
        1. 6.4.5.1 Voltage Margining and Scaling
          1. 6.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.5.1.2 Programmable Slew-Rate Control
          3. 6.4.5.1.3 PMBus Compatibility Mode
        2. 6.4.5.2 Function Generation
          1. 6.4.5.2.1 Triangular Waveform Generation
          2. 6.4.5.2.2 Sawtooth Waveform Generation
          3. 6.4.5.2.3 Sine Waveform Generation
      6. 6.4.6 Device Reset and Fault Management
        1. 6.4.6.1 Power-On Reset (POR)
        2. 6.4.6.2 External Reset
        3. 6.4.6.3 Register-Map Lock
        4. 6.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 6.4.7 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
      3. 6.5.3 General-Purpose Input/Output (GPIO) Modes
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
    3. 7.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
    4. 7.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
    5. 7.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
    6. 7.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
    7. 7.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
    8. 7.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
    9. 7.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    10. 7.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    11. 7.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    12. 7.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
    13. 7.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
    14. 7.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    15. 7.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    16. 7.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    17. 7.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    18. 7.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    19. 7.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
    20. 7.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
    21. 7.21 PMBUS-PAGE Register [reset = 0300h]
    22. 7.22 PMBUS-OP-CMD-X Register [reset = 0000h]
    23. 7.23 PMBUS-CML Register [reset = 0000h]
    24. 7.24 PMBUS-VERSION Register [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5.2.3 I2C Read Sequence

To read any register the following command sequence must be used:

  1. Send a start or repeated start command with a target address and the R/W bit set to 0 for writing. The device acknowledges this event.
  2. Send a command byte for the register to be read. The device acknowledges this event again.
  3. Send a repeated start with the target address and the R/W bit set to 1 for reading. The device acknowledges this event.
  4. The device writes the MSDB byte of the addressed register. The controller must acknowledge this byte.
  5. Finally, the device writes out the LSDB of the register.

The broadcast address cannot be used for reading.

Table 6-17 Read Sequence
S MSB … R/W (0) ACK MSB … LSB ACK Sr MSB … R/W (1) ACK MSB … LSB ACK MSB … LSB ACK
ADDRESS BYTE
Section 6.5.2.2.1		 COMMAND BYTE
Section 6.5.2.2.2		 Sr ADDRESS BYTE
Section 6.5.2.2.1		 MSDB LSDB
From Controller Target From Controller Target From Controller Target From Target Controller From Target Controller