SLASF73A April   2023  – July 2025 DAC63202W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: General
    9. 5.9  Timing Requirements: I2C Standard Mode
    10. 5.10 Timing Requirements: I2C Fast Mode
    11. 5.11 Timing Requirements: I2C Fast Mode Plus
    12. 5.12 Timing Requirements: SPI Write Operation
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 5.15 Timing Requirements: GPIO
    16. 5.16 Timing Diagrams
    17. 5.17 Typical Characteristics: Voltage Output
    18. 5.18 Typical Characteristics: Current Output
    19. 5.19 Typical Characteristics: Comparator
    20. 5.20 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 External Reference
          3. 6.4.1.1.3 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Fault-Dump Mode
      5. 6.4.5 Application-Specific Modes
        1. 6.4.5.1 Voltage Margining and Scaling
          1. 6.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.5.1.2 Programmable Slew-Rate Control
          3. 6.4.5.1.3 PMBus Compatibility Mode
        2. 6.4.5.2 Function Generation
          1. 6.4.5.2.1 Triangular Waveform Generation
          2. 6.4.5.2.2 Sawtooth Waveform Generation
          3. 6.4.5.2.3 Sine Waveform Generation
      6. 6.4.6 Device Reset and Fault Management
        1. 6.4.6.1 Power-On Reset (POR)
        2. 6.4.6.2 External Reset
        3. 6.4.6.3 Register-Map Lock
        4. 6.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 6.4.7 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
      3. 6.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 6.6 Register Map
      1. 6.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 6.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 6.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 6.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 6.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 6.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 6.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 6.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 6.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 6.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 6.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 6.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 6.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 6.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 6.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 6.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 6.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 6.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 6.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 6.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 6.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 6.6.22 PMBUS-CML Register [reset = 0000h]
      23. 6.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.18 Typical Characteristics: Current Output

at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)

DAC63202W Current Output INL vs Digital Input Code
 
Figure 5-30 Current Output INL vs Digital Input Code
DAC63202W Current Output INL vs Supply Voltage
 
Figure 5-32 Current Output INL vs Supply Voltage
DAC63202W Current Output DNL vs Temperature
 
Figure 5-34 Current Output DNL vs Temperature
DAC63202W Current Output TUE vs Digital Input Code
 
Figure 5-36 Current Output TUE vs Digital Input Code
DAC63202W Current Output TUE vs Supply Voltage
DAC channels at midscale
Figure 5-38 Current Output TUE vs Supply Voltage
DAC63202W Current Output Gain Error vs Temperature
 
Figure 5-40 Current Output Gain Error vs Temperature
DAC63202W Current Output Setting Time, Rising Edge
 
Figure 5-42 Current Output Setting Time, Rising Edge
DAC63202W Current Output Power-On Glitch
DAC at mid scale (0 μA) stored in EEPROM
Figure 5-44 Current Output Power-On Glitch
DAC63202W Current Output Noise Density
 
Figure 5-46 Current Output Noise Density
DAC63202W Current Output AC PSRR vs Frequency
 
Figure 5-48 Current Output AC PSRR vs Frequency
DAC63202W Current Output INL vs Temperature
 
Figure 5-31 Current Output INL vs Temperature
DAC63202W Current Output DNL vs Digital Input Code
 
Figure 5-33 Current Output DNL vs Digital Input Code
DAC63202W Current Output DNL vs Supply Voltage
 
Figure 5-35 Current Output DNL vs Supply Voltage
DAC63202W Current Output TUE vs Temperature
DAC channels at midscale
Figure 5-37 Current Output TUE vs Temperature
DAC63202W Current Output Offset Error vs Temperature
 
Figure 5-39 Current Output Offset Error vs Temperature
DAC63202W Current Output vs Load Voltage
 
Figure 5-41 Current Output vs Load Voltage
DAC63202W Current Output Setting Time, Falling Edge
 
Figure 5-43 Current Output Setting Time, Falling Edge
DAC63202W Current Output Power-Off Glitch
DAC at mid scale (0 μA)
Figure 5-45 Current Output Power-Off Glitch
DAC63202W Current Output Flicker Noise
f = 0.1 Hz to 10 Hz
Figure 5-47 Current Output Flicker Noise