SLASFA6B November   2024  – October 2025 MSPM0G3518-Q1 , MSPM0G3519-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 DAC
    18. 8.18 Security
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC-P
    23. 8.23 MATHACL
    24. 8.24 UART
    25. 8.25 I2C
    26. 8.26 SPI
    27. 8.27 CAN-FD
    28. 8.28 Low-Frequency Sub System (LFSS)
    29. 8.29 RTC_B
    30. 8.30 IWDT_B
    31. 8.31 WWDT
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tray Information
    2.     PACKAGE OPTION ADDENDUM

5 Device Comparison

The following table summarizes the features of each device that is described in this data sheet.

Table 5-1 Device Comparison Table

DEVICE NAME(1)(4)

FLASH / SRAM (KB)

QUAL(2)

CAN

UART/I2C/SPI

ADC / CHAN

GPIO

PACKAGE(3)

M0G3518QPZRQ1

256 / 128

Q

2

7 / 3 / 3

2 / 27

94

100 LQFP
(0.5mm pitch)
[16mm x 16mm]

M0G3519QPZRQ1

512 / 128

Q

2

7 / 3 / 3

2 / 27

94

M0G3518QPNRQ1

256 / 128

Q

2

7 / 3 / 3

2 / 27

74

80 LQFP
(0.5mm pitch)
[14mm x 14mm]

M0G3519QPNRQ1

512 / 128

Q

2

7 / 3 / 3

2 / 27

74

M0G3518QPMRQ1

256 / 128

Q

2

7 / 3 / 3

2 / 27

60

64 LQFP
(0.5mm pitch)
[12mm x 12mm]

M0G3519QPMRQ1

512 / 128

Q

2

7 / 3 / 3

2 / 27

60

M0G3519AQPMRQ1(6)512 / 128Q27 / 3 / 32 / 2760

M0G3518QPTRQ1

256 / 128

Q

1

6 / 3 / 2

2 / 21

44

48 LQFP
(0.5mm pitch)
[9mm x 9mm]

M0G3519QPTRQ1

512 / 128

Q

1

6 / 3 / 2

2 / 21

44

M0G3518QRGZRQ1

256 / 128

Q

1

6 / 3 / 2

2 / 21

44

48 VQFN
(0.5mm pitch)
[7mm x 7mm](5)

M0G3519QRGZRQ1

512 / 128

Q

1

6 / 3 / 2

2 / 21

44

M0G3518QRHBRQ1

256 / 128

Q

1

5 / 3 / 2

2 / 16

28

32 VQFN
(0.5mm pitch)
[5mm x 5mm](5)

M0G3519QRHBRQ1

512 / 128

Q

1

5 / 3 / 2

2 / 16

28

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 12, or see the TI website.
(2) Device Qualifications:
  • Q = –40°C to 125°C, AEC-Q100 qualified
(3) The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section 12.
(4) For more information about the device name, see Section 10.2
(5) 32 and 48-pin VQFN packages are available with wettable flanks
(6) M0G3519AQPMRQ1 device variant is configured for faster LFXT start-up timing