SLAU923B June   2025  – April 2026 MSPM0H3216

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Fast Boot
      3. 1.4.3 NONMAIN Layout Types
      4. 1.4.4 NONMAIN_TYPED Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Peripheral Enable
        1. 2.2.5.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Shutdown Mode Handling (if present)
      7. 2.4.7  Configuration Lockout
      8. 2.4.8  System Status
      9. 2.4.9  Error Handling
      10. 2.4.10 SYSCTL Events
        1. 2.4.10.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.10.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL_H3215_H3216 Registers
    6. 2.6 Quick Start Reference
      1. 2.6.1 Default Device Configuration
      2. 2.6.2 Leveraging MFCLK
      3. 2.6.3 Optimizing Power Consumption in STOP Mode
      4. 2.6.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.6.5 Increasing MCLK Precision
      6. 2.6.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.6.7 Optimizing for Lowest Wakeup Latency
      8. 2.6.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Window Comparator
        2. 10.2.12.2 DMA and FIFO Operation
        3. 10.2.12.3 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11VREF
    1. 11.1 VREF Overview
    2. 11.2 VREF Operation
      1. 11.2.1 Internal Reference Generation
      2. 11.2.2 External Reference Input
      3. 11.2.3 Analog Peripheral Interface
    3. 11.3 VREF Registers
  14. 12UART
    1. 12.1 UART Overview
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 Features
      3. 12.1.3 Functional Block Diagram
    2. 12.2 UART Operation
      1. 12.2.1 Clock Control
      2. 12.2.2 Signal Descriptions
      3. 12.2.3 General Architecture and Protocol
        1. 12.2.3.1  Transmit Receive Logic
        2. 12.2.3.2  Bit Sampling
        3. 12.2.3.3  Majority Voting Feature
        4. 12.2.3.4  Baud Rate Generation
        5. 12.2.3.5  Data Transmission
        6. 12.2.3.6  Error and Status
        7. 12.2.3.7  Local Interconnect Network (LIN) Support
          1. 12.2.3.7.1 LIN Responder Transmission Delay
        8. 12.2.3.8  Flow Control
        9. 12.2.3.9  Idle-Line Multiprocessor
        10. 12.2.3.10 9-Bit UART Mode
        11. 12.2.3.11 RS-485 Support
        12. 12.2.3.12 DALI Protocol
        13. 12.2.3.13 Manchester Encoding and Decoding
        14. 12.2.3.14 IrDA Encoding and Decoding
        15. 12.2.3.15 ISO7816 Smart Card Support
        16. 12.2.3.16 Address Detection
        17. 12.2.3.17 FIFO Operation
        18. 12.2.3.18 Loopback Operation
        19. 12.2.3.19 Glitch Suppression
      4. 12.2.4 Low Power Operation
      5. 12.2.5 Reset Considerations
      6. 12.2.6 Initialization
      7. 12.2.7 Interrupt and Events Support
        1. 12.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 12.2.8 Emulation Modes
    3. 12.3 UART Registers
  15. 13SPI
    1. 13.1 SPI Overview
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 External Connections and Signal Descriptions
    2. 13.2 SPI Operation
      1. 13.2.1 Clock Control
      2. 13.2.2 General Architecture
        1. 13.2.2.1 Chip Select and Command Handling
          1. 13.2.2.1.1 Chip Select Control
          2. 13.2.2.1.2 Command Data Control
        2. 13.2.2.2 Data Format
        3. 13.2.2.3 Delayed data sampling
        4. 13.2.2.4 Clock Generation
        5. 13.2.2.5 FIFO Operation
        6. 13.2.2.6 Loopback mode
        7. 13.2.2.7 DMA Operation
        8. 13.2.2.8 Repeat Transfer mode
        9. 13.2.2.9 Low Power Mode
      3. 13.2.3 Protocol Descriptions
        1. 13.2.3.1 Motorola SPI Frame Format
        2. 13.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 13.2.4 Reset Considerations
      5. 13.2.5 Initialization
      6. 13.2.6 Interrupt and Events Support
        1. 13.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 13.2.7 Emulation Modes
    3. 13.3 SPI Registers
  16. 14I2C
    1. 14.1 I2C Overview
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Environment and External Connections
    2. 14.2 I2C Operation
      1. 14.2.1 Clock Control
        1. 14.2.1.1 Clock Select and I2C Speed
        2. 14.2.1.2 Clock Startup
      2. 14.2.2 Signal Descriptions
      3. 14.2.3 General Architecture
        1. 14.2.3.1  I2C Bus Functional Overview
        2. 14.2.3.2  START and STOP Conditions
        3. 14.2.3.3  Data Format with 7-Bit Address
        4. 14.2.3.4  Data Format with 10-Bit Address
        5. 14.2.3.5  Acknowledge
        6. 14.2.3.6  Repeated Start
        7. 14.2.3.7  SCL Clock Low Timeout
        8. 14.2.3.8  Clock Stretching
        9. 14.2.3.9  Dual Address
        10. 14.2.3.10 Arbitration
        11. 14.2.3.11 Multiple Controller Mode
        12. 14.2.3.12 Glitch Suppression
        13. 14.2.3.13 FIFO operation
          1. 14.2.3.13.1 Flushing Stale Tx Data in Target Mode
        14. 14.2.3.14 Loopback mode
        15. 14.2.3.15 Burst Mode
        16. 14.2.3.16 DMA Operation
        17. 14.2.3.17 Low-Power Operation
      4. 14.2.4 Protocol Descriptions
        1. 14.2.4.1 I2C Controller Mode
          1. 14.2.4.1.1 Controller Configuration
          2. 14.2.4.1.2 Controller Mode Operation
          3. 14.2.4.1.3 Read On TX Empty
        2. 14.2.4.2 I2C Target Mode
          1. 14.2.4.2.1 Target Mode Operation
      5. 14.2.5 Reset Considerations
      6. 14.2.6 Initialization
      7. 14.2.7 Interrupt and Events Support
        1. 14.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 14.2.8 Emulation Modes
    3. 14.3 I2C Registers
  17. 15CRC
    1. 15.1 CRC Overview
      1. 15.1.1 CRC16-CCITT
    2. 15.2 CRC Operation
      1. 15.2.1 CRC Generator Implementation
      2. 15.2.2 Configuration
        1. 15.2.2.1 Bit Order
        2. 15.2.2.2 Byte Swap
        3. 15.2.2.3 Byte Order
        4. 15.2.2.4 CRC C Library Compatibility
    3. 15.3 CRCP0 Registers
  18. 16Temperature Sensor
  19. 17Timers (TIMx)
    1. 17.1 TIMx Overview
      1. 17.1.1 TIMG Overview
        1. 17.1.1.1 TIMG Features
        2. 17.1.1.2 Functional Block Diagram
      2. 17.1.2 TIMA Overview
        1. 17.1.2.1 TIMA Features
        2. 17.1.2.2 Functional Block Diagram
      3. 17.1.3 TIMx Instance Configuration
    2. 17.2 TIMx Operation
      1. 17.2.1  Timer Counter
        1. 17.2.1.1 Clock Source Select and Prescaler
          1. 17.2.1.1.1 Internal Clock and Prescaler
          2. 17.2.1.1.2 External Signal Trigger
        2. 17.2.1.2 Repeat Counter (TIMA only)
      2. 17.2.2  Counting Mode Control
        1. 17.2.2.1 One-shot and Periodic Modes
        2. 17.2.2.2 Down Counting Mode
        3. 17.2.2.3 Up/Down Counting Mode
        4. 17.2.2.4 Up Counting Mode
        5. 17.2.2.5 Phase Load (TIMA only)
      3. 17.2.3  Capture/Compare Module
        1. 17.2.3.1 Capture Mode
          1. 17.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 17.2.3.1.1.1 CCP Input Edge Synchronization
            2. 17.2.3.1.1.2 CCP Input Pulse Conditions
            3. 17.2.3.1.1.3 Counter Control Operation
            4. 17.2.3.1.1.4 CCP Input Filtering
            5. 17.2.3.1.1.5 Input Selection
          2. 17.2.3.1.2 Use Cases
            1. 17.2.3.1.2.1 Edge Time Capture
            2. 17.2.3.1.2.2 Period Capture
            3. 17.2.3.1.2.3 Pulse Width Capture
            4. 17.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 17.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 17.2.3.1.3.1 QEI With 2-Signal
            2. 17.2.3.1.3.2 QEI With Index Input
            3. 17.2.3.1.3.3 QEI Error Detection
          4. 17.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 17.2.3.2 Compare Mode
          1. 17.2.3.2.1 Edge Count
      4. 17.2.4  Shadow Load and Shadow Compare
        1. 17.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 17.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 17.2.5  Output Generator
        1. 17.2.5.1 Configuration
        2. 17.2.5.2 Use Cases
          1. 17.2.5.2.1 Edge-Aligned PWM
          2. 17.2.5.2.2 Center-Aligned PWM
          3. 17.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 17.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 17.2.5.3 Forced Output
      6. 17.2.6  Fault Handler (TIMA only)
        1. 17.2.6.1 Fault Input Conditioning
        2. 17.2.6.2 Fault Input Sources
        3. 17.2.6.3 Counter Behavior With Fault Conditions
        4. 17.2.6.4 Output Behavior With Fault Conditions
      7. 17.2.7  Synchronization With Cross Trigger
        1. 17.2.7.1 Main Timer Cross Trigger Configuration
        2. 17.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 17.2.8  Low Power Operation
      9. 17.2.9  Interrupt and Event Support
        1. 17.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 17.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 17.2.10 Debug Handler (TIMA Only)
    3. 17.3 TIMx Registers
  20. 18Low Frequency Subsystem (LFSS_B)
    1. 18.1 Overview
    2. 18.2 Clock System
    3. 18.3 LFSS Reset
    4. 18.4 Real Time Counter (RTC_x)
    5. 18.5 Independent Watchdog Timer (IWDT)
    6. 18.6 Lock Function of RTC and IWDT
    7. 18.7 LFSS Registers
  21. 19RTC
    1. 19.1 Overview
      1. 19.1.1 RTC Instances
    2. 19.2 Basic Operation
    3. 19.3 Configuration
      1. 19.3.1  Clocking
      2. 19.3.2  Reading and Writing to RTC Peripheral Registers
      3. 19.3.3  Binary vs. BCD
      4. 19.3.4  Leap Year Handling
      5. 19.3.5  Calendar Alarm Configuration
      6. 19.3.6  Interval Alarm Configuration
      7. 19.3.7  Periodic Alarm Configuration
      8. 19.3.8  Calibration
        1. 19.3.8.1 Crystal Offset Error
          1. 19.3.8.1.1 Offset Error Correction Mechanism
        2. 19.3.8.2 Crystal Temperature Error
          1. 19.3.8.2.1 Temperature Drift Correction Mechanism
      9. 19.3.9  RTC Prescaler Extension
      10. 19.3.10 RTC Timestamp Capture
      11. 19.3.11 RTC Events
        1. 19.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 19.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 19.4 RTC Registers
  22. 20IWDT
    1. 20.1 542
    2. 20.2 IWDT Clock Configuration
    3. 20.3 IWDT Period Selection
    4. 20.4 Debug Behavior of the IWDT
    5. 20.5 IWDT Registers
  23. 21Window Watchdog Timer (WWDT)
    1. 21.1 WWDT Overview
      1. 21.1.1 Watchdog Mode
      2. 21.1.2 Interval Timer Mode
    2. 21.2 WWDT Operation
      1. 21.2.1 Mode Selection
      2. 21.2.2 Clock Configuration
      3. 21.2.3 Low-Power Mode Behavior
      4. 21.2.4 Debug Behavior
      5. 21.2.5 WWDT Events
        1. 21.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 21.3 WWDT Registers
  24. 22Debug
    1. 22.1 DEBUGSS Overview
      1. 22.1.1 Debug Interconnect
      2. 22.1.2 Physical Interface
      3. 22.1.3 Debug Access Ports
    2. 22.2 DEBUGSS Operation
      1. 22.2.1 Debug Features
        1. 22.2.1.1 Processor Debug
          1. 22.2.1.1.1 Breakpoint Unit (BPU)
          2. 22.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 22.2.1.2 Peripheral Debug
        3. 22.2.1.3 EnergyTrace Technology
      2. 22.2.2 Behavior in Low Power Modes
      3. 22.2.3 Restricting Debug Access
      4. 22.2.4 Mailbox (DSSM)
        1. 22.2.4.1 DSSM Events
          1. 22.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 22.2.4.2 Reference
    3. 22.3 DEBUGSS Registers
  25. 23Revision History

2.5 SYSCTL_H3215_H3216 Registers

Table 2-14 lists the memory-mapped registers for the SYSCTL_H3215_H3216 registers. All register offset addresses not listed in Table 2-14 should be considered as reserved locations and the register contents should not be modified.

Table 2-14 SYSCTL_H3215_H3216 Registers
OffsetAcronymRegister NameSection
1020hIIDXSYSCTL interrupt indexSection 2.5.1
1028hIMASKSYSCTL interrupt maskSection 2.5.2
1030hRISSYSCTL raw interrupt statusSection 2.5.3
1038hMISSYSCTL masked interrupt statusSection 2.5.4
1040hISETSYSCTL interrupt setSection 2.5.5
1048hICLRSYSCTL interrupt clearSection 2.5.6
1050hNMIIIDXNMI interrupt indexSection 2.5.7
1060hNMIRISNMI raw interrupt statusSection 2.5.8
1070hNMIISETNMI interrupt setSection 2.5.9
1078hNMIICLRNMI interrupt clearSection 2.5.10
1100hSYSOSCCFGSYSOSC configurationSection 2.5.11
1104hMCLKCFGMain clock (MCLK) configurationSection 2.5.12
1108hHSCLKENHigh-speed clock (HSCLK) source enable/disableSection 2.5.13
110ChHSCLKCFGHigh-speed clock (HSCLK) source selectionSection 2.5.14
1110hHFCLKCLKCFGHigh-frequency clock (HFCLK) configurationSection 2.5.15
1114hLFCLKCFGLow frequency crystal oscillator (LFXT) configurationSection 2.5.16
1138hGENCLKCFGGeneral clock configurationSection 2.5.17
113ChGENCLKENGeneral clock enable controlSection 2.5.18
1140hPMODECFGPower mode configurationSection 2.5.19
1150hFCCFrequency clock counter (FCC) countSection 2.5.20
1178hSRAMBOUNDARYSRAM Write BoundarySection 2.5.21
1180hSYSTEMCFGSystem configurationSection 2.5.22
1190hBEEPCFGBEEPER ConfigurationSection 2.5.23
1200hWRITELOCKSYSCTL register write lockoutSection 2.5.24
1204hCLKSTATUSClock module (CKM) statusSection 2.5.25
1208hSYSSTATUSSystem status informationSection 2.5.26
1220hRSTCAUSEReset causeSection 2.5.27
1300hRESETLEVELReset level for application-triggered reset commandSection 2.5.28
1304hRESETCMDExecute an application-triggered reset commandSection 2.5.29
1308hBORTHRESHOLDBOR threshold selectionSection 2.5.30
130ChBORCLRCMDSet the BOR thresholdSection 2.5.31
1310hSYSOSCFCLCTLSYSOSC frequency correction loop (FCL) ROSC enableSection 2.5.32
1314hLFXTCTLLFXT and LFCLK controlSection 2.5.33
1318hEXLFCTLLFCLK_IN and LFCLK controlSection 2.5.34
1320hEXRSTPINDisable the reset function of the NRST pinSection 2.5.35
1324hSYSSTATUSCLRClear sticky bits of SYSSTATUSSection 2.5.36
1328hSWDCFGDisable the SWD function on the SWD pinsSection 2.5.37
132ChFCCCMDFrequency clock counter start captureSection 2.5.38

Complex bit access types are encoded to fit into small table cells. Table 2-15 shows the codes that are used for access types in this section.

Table 2-15 SYSCTL_H3215_H3216 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

2.5.1 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Table 2-16.

Return to the Summary Table.

SYSCTL interrupt index

Table 2-16 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0STATR0hThe SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
  • 0h = No interrupt pending
  • 1h = LFOSCGOOD interrupt pending
  • 2h = 2
  • 3h = 3
  • 4h = 4
  • 5h = 5

2.5.2 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Table 2-17.

Return to the Summary Table.

SYSCTL interrupt mask

Table 2-17 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4HSCLKGOODR/W0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
3HFCLKGOODR/W0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
2LFXTGOODR/W0hLFXT GOOD
  • 0h = 0
  • 1h = 1
1ANACLKERRR/W0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR/W0hEnable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
  • 0h = Interrupt disabled
  • 1h = Interrupt enabled

2.5.3 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Table 2-18.

Return to the Summary Table.

SYSCTL raw interrupt status

Table 2-18 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4HSCLKGOODR0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
3HFCLKGOODR0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
2LFXTGOODR0hLFXT GOOD
  • 0h = 0
  • 1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR0hRaw status of the LFOSCGOOD interrupt.
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.5.4 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Table 2-19.

Return to the Summary Table.

SYSCTL masked interrupt status

Table 2-19 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4HSCLKGOODR0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
3HFCLKGOODR0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
2LFXTGOODR0hLFXT GOOD
  • 0h = 0
  • 1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR0hMasked status of the LFOSCGOOD interrupt.
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.5.5 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Table 2-20.

Return to the Summary Table.

SYSCTL interrupt set

Table 2-20 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDW0h
4HSCLKGOODW1S0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
3HFCLKGOODW1S0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
2LFXTGOODW1S0hLFXT GOOD
  • 0h = 0
  • 1h = 1
1ANACLKERRW1S0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODW1S0hSet the LFOSCGOOD interrupt.
  • 0h = Writing 0h hs no effect
  • 1h = Set interrupt

2.5.6 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Table 2-21.

Return to the Summary Table.

SYSCTL interrupt clear

Table 2-21 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDW0h
4HSCLKGOODW1C0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
3HFCLKGOODW1C0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
2LFXTGOODW1C0hLFXT GOOD
  • 0h = 0
  • 1h = 1
1ANACLKERRW1C0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODW1C0hClear the LFOSCGOOD interrupt.
  • 0h = Writing 0h has no effect
  • 1h = Clear interrupt

2.5.7 NMIIIDX Register (Offset = 1050h) [Reset = 00000000h]

NMIIIDX is shown in Table 2-22.

Return to the Summary Table.

NMI interrupt index

Table 2-22 NMIIIDX Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0STATR0hThe NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
  • 0h = No NMI pending
  • 1h = BOR Threshold NMI pending
  • 2h = 2
  • 3h = 3

2.5.8 NMIRIS Register (Offset = 1060h) [Reset = 00000000h]

NMIRIS is shown in Table 2-23.

Return to the Summary Table.

NMI raw interrupt status

Table 2-23 NMIRIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2LFCLKFAILR0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
1WWDT0R0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLR0hRaw status of the BORLVL NMI
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.5.9 NMIISET Register (Offset = 1070h) [Reset = 00000000h]

NMIISET is shown in Table 2-24.

Return to the Summary Table.

NMI interrupt set

Table 2-24 NMIISET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDW0h
2LFCLKFAILW1S0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
1WWDT0W1S0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLW1S0hSet the BORLVL NMI
  • 0h = Writing 0h hs no effect
  • 1h = Set interrupt

2.5.10 NMIICLR Register (Offset = 1078h) [Reset = 00000000h]

NMIICLR is shown in Table 2-25.

Return to the Summary Table.

NMI interrupt clear

Table 2-25 NMIICLR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDW0h
2LFCLKFAILW1C0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
1WWDT0W1C0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLW1C0hClr the BORLVL NMI
  • 0h = Writing 0h hs no effect
  • 1h = Clear interrupt

2.5.11 SYSOSCCFG Register (Offset = 1100h) [Reset = 0002XXXXh]

SYSOSCCFG is shown in Table 2-26.

Return to the Summary Table.

SYSOSC configuration

Table 2-26 SYSOSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0h
17FASTCPUEVENTR/W1hFASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.
  • 0h = An interrupt to the CPU will not assert a fast clock request
  • 1h = An interrupt to the CPU will assert a fast clock request
16BLOCKASYNCALLR/W0hBLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
  • 0h = Asynchronous fast clock requests are controlled by the requesting peripheral
  • 1h = All asynchronous fast clock requests are blocked
15-11RESERVEDR/W0h
10DISABLER/W0hDISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.
  • 0h = Do not disable SYSOSC
  • 1h = Disable SYSOSC immediately and source MCLK and ULPCLK from LFCLK
9DISABLESTOPR/W0hDISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.
  • 0h = Do not disable SYSOSC in STOP mode
  • 1h = Disable SYSOSC in STOP mode and source ULPCLK from LFCLK
8-2RESERVEDR/W0h
1-0FREQR/W0hTarget operating frequency for the system oscillator (SYSOSC)
  • 0h = Base frequency (32MHz)
  • 1h = Low frequency (4MHz)
  • 2h = User-trimmed frequency (16 or 24 MHz)

2.5.12 MCLKCFG Register (Offset = 1104h) [Reset = 000XX2X0h]

MCLKCFG is shown in Table 2-27.

Return to the Summary Table.

Main clock (MCLK) configuration

Table 2-27 MCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR/W0h
22MCLKDEADCHKR/W0hMCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled.
  • 0h = The MCLK dead check monitor is disabled
  • 1h = The MCLK dead check monitor is enabled
21STOPCLKSTBYR/W0hSTOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request.
  • 0h = ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode
  • 1h = ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1
20USELFCLKR/W0hUSELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source. Note that setting USELFCLK does not disable SYSOSC, and SYSOSC remains available for direct use by analog modules.
  • 0h = MCLK will not use the low frequency clock (LFCLK)
  • 1h = MCLK will use the low frequency clock (LFCLK)
19-17RESERVEDR/W0h
16USEHSCLKR/W0hUSEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes.
  • 0h = MCLK will not use the high speed clock (HSCLK)
  • 1h = MCLK will use the high speed clock (HSCLK) in RUN and SLEEP mode
15-13RESERVEDR/W0h
12USEMFTICKR/W0hUSEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1).
  • 0h = The 4MHz rate MFCLK to peripherals is disabled.
  • 1h = The 4MHz rate MFCLK to peripherals is enabled.
11-8FLASHWAITR/W2hFLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK.
  • 0h = No flash wait states are applied
  • 1h = One flash wait state is applied
  • 2h = 2 flash wait states are applied
7-4RESERVEDR/W0h
3-0MDIVR/W0hMDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC. MDIV=0h corresponds to /1 (no divider). MDIV=1h corresponds to /2 (divide-by-2). MDIV=Fh corresponds to /16 (divide-by-16). MDIV may be set between /1 and /16 on an integer basis.

2.5.13 HSCLKEN Register (Offset = 1108h) [Reset = 0000XXXXh]

HSCLKEN is shown in Table 2-28.

Return to the Summary Table.

High-speed clock (HSCLK) source enable/disable

Table 2-28 HSCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/W0h
16USEEXTHFCLKR/W0hUSEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled, HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously.
  • 0h = Use HFXT as the HFCLK source
  • 1h = Use the HFCLK_IN digital clock input as the HFCLK source
15-1RESERVEDR/W0h
0HFXTENR/W0hHFXTEN enables or disables the high frequency crystal oscillator (HFXT).
  • 0h = Disable the HFXT
  • 1h = Enable the HFXT

2.5.14 HSCLKCFG Register (Offset = 110Ch) [Reset = 00000000h]

HSCLKCFG is shown in Table 2-29.

Return to the Summary Table.

High-speed clock (HSCLK) source selection

Table 2-29 HSCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0HSCLKSELR/W0hHSCLKSEL selects the HSCLK source (SYSPLL or HFCLK).
  • 1h = HSCLK is sourced from the HFCLK

2.5.15 HFCLKCLKCFG Register (Offset = 1110h) [Reset = 1XXXXX00h]

HFCLKCLKCFG is shown in Table 2-30.

Return to the Summary Table.

High-frequency clock (HFCLK) configuration

Table 2-30 HFCLKCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28HFCLKFLTCHKR/W1hHFCLKFLTCHK enables or disables the HFCLK startup monitor.
  • 0h = HFCLK startup is not checked
  • 1h = HFCLK startup is checked
27-14RESERVEDR/W0h
13-12HFXTRSELR/W0hHFXT Range Select
  • 0h = 4MHz <= HFXT frequency <= 8MHz
  • 1h = 8MHz < HFXT frequency <= 16MHz
  • 2h = 16MHz < HFXT frequency <= 32MHz
  • 3h = 32MHz < HFXT frequency <= 48MHz
11-8RESERVEDR/W0h
7-0HFXTTIMER/W0hHFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time expires.
  • 0h = Minimum startup time (approximatly zero)
  • FFh = Maximum startup time (approximatly 16.32ms)

2.5.16 LFCLKCFG Register (Offset = 1114h) [Reset = 000000XXh]

LFCLKCFG is shown in Table 2-31.

Return to the Summary Table.

Low frequency crystal oscillator (LFXT) configuration

Table 2-31 LFCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8LOWCAPR/W0hLOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf, LOWCAP may be set for reduced power consumption.
  • 0h = LFXT low capacitance mode is disabled
  • 1h = LFXT low capacitance mode is enabled
7-5RESERVEDR/W0h
4MONITORR/W0hMONITOR enables or disables the LFCLK monitor, which continuously checks LFXT or LFCLK_IN for a clock stuck fault.
  • 0h = Clock monitor is disabled
  • 1h = Clock monitor is enabled
3-2RESERVEDR/W0h
1-0XT1DRIVER/W3hXT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength.
  • 0h = Lowest drive and current
  • 1h = Lower drive and current
  • 2h = Higher drive and current
  • 3h = Highest drive and current

2.5.17 GENCLKCFG Register (Offset = 1138h) [Reset = 00000X0Xh]

GENCLKCFG is shown in Table 2-32.

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General clock configuration

Table 2-32 GENCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29FCCLFCLKSRCR/W0hFCCLFCLKSRC selects between SYSTEM LFCLK and EXTERNAL SOURCED LFCLK.
28-24FCCTRIGCNTR/W0hFCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified.
23-22ANACPUMPCFGR/W0hANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method.
  • 0h = VBOOST is enabled on request from a COMP, GPAMP, or OPA
  • 1h = VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled
  • 2h = VBOOST is always enabled
21FCCLVLTRIGR/W0hFCCLVLTRIG selects the frequency clock counter (FCC) trigger mode.
  • 0h = Rising edge to rising edge triggered
  • 1h = Level triggered
20FCCTRIGSRCR/W0hFCCTRIGSRC selects the frequency clock counter (FCC) trigger source.
  • 0h = FCC trigger is the external pin
  • 1h = FCC trigger is the LFCLK
19-16FCCSELCLKR/W0hFCCSELCLK selectes the frequency clock counter (FCC) clock source.
  • 0h = FCC clock is MCLK
  • 1h = FCC clock is SYSOSC
  • 2h = FCC clock is HFCLK
  • 3h = FCC clock is the CLK_OUT selection
  • 7h = FCC clock is the FCCIN external input
15-12HFCLK4MFPCLKDIVR/W0hHFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected.
  • 0h = HFCLK is not divided before being used for MFPCLK
  • 1h = HFCLK is divided by 2 before being used for MFPCLK
  • 2h = HFCLK is divided by 3 before being used for MFPCLK
  • 3h = HFCLK is divided by 4 before being used for MFPCLK
  • 4h = HFCLK is divided by 5 before being used for MFPCLK
  • 5h = HFCLK is divided by 6 before being used for MFPCLK
  • 6h = HFCLK is divided by 7 before being used for MFPCLK
  • 7h = HFCLK is divided by 8 before being used for MFPCLK
  • 8h = HFCLK is divided by 9 before being used for MFPCLK
  • 9h = HFCLK is divided by 10 before being used for MFPCLK
  • Ah = HFCLK is divided by 11 before being used for MFPCLK
  • Bh = HFCLK is divided by 12 before being used for MFPCLK
  • Ch = HFCLK is divided by 13 before being used for MFPCLK
  • Dh = HFCLK is divided by 14 before being used for MFPCLK
  • Eh = HFCLK is divided by 15 before being used for MFPCLK
  • Fh = HFCLK is divided by 16 before being used for MFPCLK
11-10RESERVEDR/W0h
9MFPCLKSRCR/W0hMFPCLKSRC selects the MFPCLK (middle frequency precision clock) source.
  • 0h = MFPCLK is sourced from SYSOSC
  • 1h = MFPCLK is sourced from HFCLK
8RESERVEDR/W0h
7EXCLKDIVENR/W0hEXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block.
  • 0h = CLock divider is disabled (passthrough, EXCLKDIVVAL is not applied)
  • 1h = Clock divider is enabled (EXCLKDIVVAL is applied)
6-4EXCLKDIVVALR/W0hEXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block.
  • 0h = CLK_OUT source is divided by 2
  • 1h = CLK_OUT source is divided by 4
  • 2h = CLK_OUT source is divided by 6
  • 3h = CLK_OUT source is divided by 8
  • 4h = CLK_OUT source is divided by 10
  • 5h = CLK_OUT source is divided by 12
  • 6h = CLK_OUT source is divided by 14
  • 7h = CLK_OUT source is divided by 16
3RESERVEDR/W0h
2-0EXCLKSRCR/W0hEXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled
  • 0h = CLK_OUT is SYSOSC
  • 1h = CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled)
  • 2h = CLK_OUT is LFCLK
  • 3h = CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled)
  • 4h = CLK_OUT is HFCLK

2.5.18 GENCLKEN Register (Offset = 113Ch) [Reset = 0000000Xh]

GENCLKEN is shown in Table 2-33.

Return to the Summary Table.

General clock enable control

Table 2-33 GENCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0h
4MFPCLKENR/W0hMFPCLKEN enables the middle frequency precision clock (MFPCLK).
  • 0h = MFPCLK is disabled
  • 1h = MFPCLK is enabled
3-1RESERVEDR/W0h
0EXCLKENR/W0hEXCLKEN enables the CLK_OUT external clock output block.
  • 0h = CLK_OUT block is disabled
  • 1h = CLK_OUT block is enabled

2.5.19 PMODECFG Register (Offset = 1140h) [Reset = 00000000h]

PMODECFG is shown in Table 2-34.

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Power mode configuration

Table 2-34 PMODECFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0DSLEEPR/W0hDSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
  • 0h = STOP mode is entered
  • 1h = STANDBY mode is entered
  • 2h = SHUTDOWN mode is entered
  • 3h = Reserved

2.5.20 FCC Register (Offset = 1150h) [Reset = 00000000h]

FCC is shown in Table 2-35.

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Frequency clock counter (FCC) count

Table 2-35 FCC Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-0DATAR0hFrequency clock counter (FCC) count value.

2.5.21 SRAMBOUNDARY Register (Offset = 1178h) [Reset = 000000XXh]

SRAMBOUNDARY is shown in Table 2-36.

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SRAM Write Boundary

Table 2-36 SRAMBOUNDARY Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-5ADDRR/W0hSRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size.
4-0RESERVEDR/W0h

2.5.22 SYSTEMCFG Register (Offset = 1180h) [Reset = 00XXXXXXh]

SYSTEMCFG is shown in Table 2-37.

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System configuration

Table 2-37 SYSTEMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0
  • 1Bh = Issue write
23-1RESERVEDR/W0h
0WWDTLP0RSTDISR/W0hWWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.
  • 0h = WWDTLP0 Error Event will trigger a BOOTRST
  • 1h = WWDTLP0 Error Event will trigger an NMI

2.5.23 BEEPCFG Register (Offset = 1190h) [Reset = 0000000Xh]

BEEPCFG is shown in Table 2-38.

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BEEPER Configuration

Table 2-38 BEEPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR/W0h
5-4FREQR/W0hBeeper Output Frequency Configuration
  • 0h = Beeper runs at 8KHz
  • 1h = Beeper runs at 4KHz
  • 2h = Beeper runs at 2KHz
  • 3h = Beeper runs at 1KHz
3-1RESERVEDR/W0h
0ENR/W0hBeeper Output Enable
  • 0h = Beeper Output Disabled
  • 1h = Beeper Output Enabled

2.5.24 WRITELOCK Register (Offset = 1200h) [Reset = 00000000h]

WRITELOCK is shown in Table 2-39.

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SYSCTL register write lockout

Table 2-39 WRITELOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0ACTIVER/W0hACTIVE controls whether critical SYSCTL registers are write protected or not.
  • 0h = Allow writes to lockable registers
  • 1h = Disallow writes to lockable registers

2.5.25 CLKSTATUS Register (Offset = 1204h) [Reset = XXXXXXXXh]

CLKSTATUS is shown in Table 2-40.

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Clock module (CKM) status

Table 2-40 CLKSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31ANACLKERRR0hANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected.
  • 0h = No analog clock errors detected
  • 1h = Analog clock error detected
30-29RESERVEDR0h
28HFCLKBLKUPDR0hHFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked.
  • 0h = Writes to HFCLKCLKCFG are allowed
  • 1h = Writes to HFCLKCLKCFG are blocked
27-26RESERVEDR0h
25FCCDONER0hFCCDONE indicates when a frequency clock counter capture is complete.
  • 0h = FCC capture is not done
  • 1h = FCC capture is done
24FCLMODER0hFCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled.
  • 0h = SYSOSC FCL is disabled
  • 1h = SYSOSC FCL is enabled
23LFCLKFAILR0hLFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure.
  • 0h = No LFCLK fault detected
  • 1h = LFCLK stuck fault detected
22RESERVEDR0h
21HSCLKGOODR0hHSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully.
  • 0h = The HSCLK source did not start correctly
  • 1h = The HSCLK source started correctly
20HSCLKDEADR0hHSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully.
  • 0h = The HSCLK source was not started or started correctly
  • 1h = The HSCLK source did not start correctly
19-18RESERVEDR0h
17CURMCLKSELR0hCURMCLKSEL indicates if MCLK is currently sourced from LFCLK.
  • 0h = MCLK is not sourced from LFCLK
  • 1h = MCLK is sourced from LFCLK
16CURHSCLKSELR0hCURHSCLKSEL indicates the current clock source for HSCLK.
  • 0h = HSCLK is currently sourced from the SYSPLL
  • 1h = HSCLK is currently sourced from the HFCLK
15-14RESERVEDR0h
13HFCLKOFFR0hHFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started, HFCLKOFF is cleared by hardware. Following startup of the HFCLK, if the HFCLK startup monitor determines that the HFCLK was not started correctly, HFCLKOFF is set.
  • 0h = HFCLK started correctly and is enabled
  • 1h = HFCLK is disabled or was dead at startup
12HSCLKSOFFR0hHSCLKSOFF is set when the high speed clock sources (SYSPLL, HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF.
  • 0h = SYSPLL, HFCLK, or both were started correctly and remain enabled
  • 1h = SYSPLL and HFCLK are both either off or dead
11LFOSCGOODR0hLFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use.
  • 0h = LFOSC is not ready
  • 1h = LFOSC is ready
10LFXTGOODR0hLFXTGOOD indicates if the LFXT started correctly. When the LFXT is started, LFXTGOOD is cleared by hardware. After the startup settling time has expired, the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set, else it is left cleared.
  • 0h = LFXT did not start correctly
  • 1h = LFXT started correctly
9RESERVEDR0h
8HFCLKGOODR0hHFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source, this bit will be set by hardware if a valid HFCLK is detected, and cleared if HFCLK is not operating within the expected range.
  • 0h = HFCLK did not start correctly
  • 1h = HFCLK started correctly
7-6LFCLKMUXR0hLFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input.
  • 0h = LFCLK is sourced from the internal LFOSC
  • 1h = LFCLK is sourced from the LFXT (crystal)
  • 2h = LFCLK is sourced from LFCLK_IN (external digital clock input)
5RESERVEDR0h
4HSCLKMUXR0hHSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK).
  • 0h = MCLK is not sourced from HSCLK
  • 1h = MCLK is sourced from HSCLK
3-2RESERVEDR0h
1-0SYSOSCFREQR0hSYSOSCFREQ indicates the current SYSOSC operating frequency.
  • 0h = SYSOSC is at base frequency (32MHz)
  • 1h = SYSOSC is at low frequency (4MHz)
  • 2h = SYSOSC is at the user-trimmed frequency (16 or 24MHz)
  • 3h = Reserved

2.5.26 SYSSTATUS Register (Offset = 1208h) [Reset = XXXX0XXXh]

SYSSTATUS is shown in Table 2-41.

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System status information

Table 2-41 SYSSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30REBOOTATTEMPTSR0hREBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts.
29-16RESERVEDR0h
15SWALTSELENR0hSWALTSELEN indicates when user has enabled the use of alternate SWD/SWCLK pins
  • 0h = Alternate SWD/SWCLK pins are disabled
  • 1h = Alternate SWD/SWCLK pins are enabled
14RESERVEDR0h
13SWDCFGDISR0hSWDCFGDIS indicates when user has disabled the use of SWD Port
  • 0h = SWD Port Enabled
  • 1h = SWD Port Disabled
12EXTRSTPINDISR0hEXTRSTPINDIS indicates when user has disabled the use of external reset pin
  • 0h = External Reset Pin Enabled
  • 1h = External Reset Pin Disabled
11-7RESERVEDR0h
6PMUIREFGOODR0hPMUIREFGOOD is set by hardware when the PMU current reference is ready.
  • 0h = IREF is not ready
  • 1h = IREF is ready
5ANACPUMPGOODR0hANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready.
  • 0h = VBOOST is not ready
  • 1h = VBOOST is ready
4BORLVLR0hBORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware.
  • 0h = No BOR violation occured
  • 1h = A BOR violation occured and the BOR threshold was switched to BOR0
3-2BORCURTHRESHOLDR0hBORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration.
  • 0h = Default minimum threshold; a BOR0- violation triggers a BOR
  • 1h = A BOR1- violation generates a BORLVL interrupt
  • 2h = A BOR2- violation generates a BORLVL interrupt
  • 3h = A BOR3- violation generates a BORLVL interrupt
1-0RESERVEDR0h

2.5.27 RSTCAUSE Register (Offset = 1220h) [Reset = 00000000h]

RSTCAUSE is shown in Table 2-42.

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Reset cause

Table 2-42 RSTCAUSE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
  • 0h = No reset since last read
  • 1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
  • 2h = NRST triggered POR (>1s hold)
  • 3h = Software triggered POR
  • 4h = BOR0- violation
  • 5h = SHUTDOWN mode exit
  • 8h = Non-PMU trim parity fault
  • 9h = Fatal clock failure
  • Ch = NRST triggered BOOTRST (<1s hold)
  • Dh = Software triggered BOOTRST
  • Eh = WWDT0 violation
  • 10h = BSL exit
  • 11h = BSL entry
  • 13h = WWDT1 violation
  • 14h = Flash uncorrectable ECC error
  • 15h = CPULOCK violation
  • 1Ah = Debug triggered SYSRST
  • 1Bh = Software triggered SYSRST
  • 1Ch = Debug triggered CPURST
  • 1Dh = Software triggered CPURST

2.5.28 RESETLEVEL Register (Offset = 1300h) [Reset = 00000000h]

RESETLEVEL is shown in Table 2-43.

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Reset level for application-triggered reset command

Table 2-43 RESETLEVEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0LEVELR/W0hLEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
  • 0h = Issue a SYSRST (CPU plus peripherals only)
  • 1h = Issue a BOOTRST (CPU, peripherals, and boot configuration routine)
  • 2h = Issue a SYSRST and enter the boot strap loader (BSL)
  • 3h = Issue a power-on reset (POR)
  • 4h = Issue a SYSRST and exit the boot strap loader (BSL)

2.5.29 RESETCMD Register (Offset = 1304h) [Reset = 00XXXXXXh]

RESETCMD is shown in Table 2-44.

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Execute an application-triggered reset command

Table 2-44 RESETCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of E4h (228) must be written to KEY together with GO to trigger the reset.
  • E4h = Issue reset
23-1RESERVEDW0h
0GOW0hExecute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
  • 1h = Issue reset

2.5.30 BORTHRESHOLD Register (Offset = 1308h) [Reset = 00000000h]

BORTHRESHOLD is shown in Table 2-45.

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BOR threshold selection

Table 2-45 BORTHRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0LEVELR/W0hLEVEL specifies the desired BOR threshold and BOR mode.
  • 0h = Default minimum threshold; a BOR0- violation triggers a BOR
  • 1h = A BOR1- violation generates a BORLVL interrupt
  • 2h = A BOR2- violation generates a BORLVL interrupt
  • 3h = A BOR3- violation generates a BORLVL interrupt

2.5.31 BORCLRCMD Register (Offset = 130Ch) [Reset = 00XXXXXXh]

BORCLRCMD is shown in Table 2-46.

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Set the BOR threshold

Table 2-46 BORCLRCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.
  • C7h = Issue clear
23-1RESERVEDW0h
0GOW0hGO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.
  • 1h = Issue clear

2.5.32 SYSOSCFCLCTL Register (Offset = 1310h) [Reset = 00XXXXXXh]

SYSOSCFCLCTL is shown in Table 2-47.

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SYSOSC frequency correction loop (FCL) ROSC enable

Table 2-47 SYSOSCFCLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
  • 2Ah = Issue Command
23-1RESERVEDW0h
0SETUSEFCLW0hSet SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.
  • 1h = Enable the SYSOSC FCL

2.5.33 LFXTCTL Register (Offset = 1314h) [Reset = 00XXXXXXh]

LFXTCTL is shown in Table 2-48.

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LFXT and LFCLK control

Table 2-48 LFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit.
  • 91h = Issue command
23-2RESERVEDW0h
1SETUSELFXTW0hSet SETUSELFXT to switch LFCLK to LFXT. Once set, SETUSELFXT remains set until the next BOOTRST.
  • 0h = 0
  • 1h = Use LFXT as the LFCLK source
0STARTLFXTW0hSet STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set, STARTLFXT remains set until the next BOOTRST.
  • 0h = LFXT not started
  • 1h = Start LFXT

2.5.34 EXLFCTL Register (Offset = 1318h) [Reset = 00XXXXXXh]

EXLFCTL is shown in Table 2-49.

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LFCLK_IN and LFCLK control

Table 2-49 EXLFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF.
  • 36h = Issue command
23-1RESERVEDW0h
0SETUSEEXLFW0hSet SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set, SETUSEEXLF remains set until the next BOOTRST.
  • 1h = Use LFCLK_IN as the LFCLK source

2.5.35 EXRSTPIN Register (Offset = 1320h) [Reset = 00XXXXXXh]

EXRSTPIN is shown in Table 2-50.

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Disable the reset function of the NRST pin

Table 2-50 EXRSTPIN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 1Eh must be written together with DISABLE to disable the reset function.
  • 1Eh = Issue command
23-1RESERVEDW0h
0DISABLEW0hSet DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
  • 0h = Reset function of NRST pin is enabled
  • 1h = Reset function of NRST pin is disabled

2.5.36 SYSSTATUSCLR Register (Offset = 1324h) [Reset = 00XXXXXXh]

SYSSTATUSCLR is shown in Table 2-51.

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Clear sticky bits of SYSSTATUS

Table 2-51 SYSSTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value CEh (206) must be written to KEY together with ALLECC to clear the ECC state.
  • CEh = Issue command
23-1RESERVEDW0h
0ALLECCW0hSet ALLECC to clear all ECC related SYSSTATUS indicators.
  • 1h = Clear ECC error state

2.5.37 SWDCFG Register (Offset = 1328h) [Reset = 00XXXXXXh]

SWDCFG is shown in Table 2-52.

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Disable the SWD function on the SWD pins

Table 2-52 SWDCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.
  • 62h = Issue command
23-1RESERVEDW0h
0DISABLEW0hSet DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.
  • 1h = Disable SWD function on SWD pins

2.5.38 FCCCMD Register (Offset = 132Ch) [Reset = 00XXXXXXh]

FCCCMD is shown in Table 2-53.

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Frequency clock counter start capture

Table 2-53 FCCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 0Eh (14) must be written with GO to start a capture.
  • 0Eh = Issue command
23-1RESERVEDW0h
0GOW0hSet GO to start a capture with the frequency clock counter (FCC).
  • 1h = 1