SLAZ146I October   2012  – May 2021 MSP430F1611

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RTD64
      2.      PM64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC18
    2. 6.2  ADC25
    3. 6.3  BCL5
    4. 6.4  CPU4
    5. 6.5  CPU41
    6. 6.6  DAC4
    7. 6.7  I2C7
    8. 6.8  I2C8
    9. 6.9  I2C9
    10. 6.10 I2C10
    11. 6.11 I2C11
    12. 6.12 I2C12
    13. 6.13 I2C13
    14. 6.14 I2C14
    15. 6.15 I2C15
    16. 6.16 I2C16
    17. 6.17 MPY2
    18. 6.18 TA12
    19. 6.19 TA16
    20. 6.20 TA21
    21. 6.21 TAB22
    22. 6.22 TB2
    23. 6.23 TB16
    24. 6.24 TB24
    25. 6.25 US14
    26. 6.26 US15
    27. 6.27 WDG2
  7. 7Revision History

6.12 I2C12

I2C Module

Category

Functional

Function

Master/Slave looses data on reception (lost RXRDYIFG).

Description

If the I2C data register I2CDRB (I2CDRW) is read at the same time that data is loaded from the internal I2C shift register into I2CDRB (I2CDRW), then the received data is lost and no corresponding receive ready interrupt (RXRDYIFG) is generated. Following RXRDYIFG interrupts are processed but the missing byte cannot be recovered.

Workaround

Do not read the I2CDRB(I2CDRW) register while data is being loaded into it. This can be ensured by reading this register in a timely manner using any one of the following methods:
1) Handle RXRDYIFG events with all other interrupt sources disabled.
2) Use the DMA for receiving incoming I2C data. The DMA interrupt or ARDYIFG interrupt can be used to initiate further processing of received data.
3) Enable nested interrupts to allow immediate processing of RXRDYIFG interrupts. (Care must be taken to avoid stack overflows).