SLAZ497H January   2013  – March 2021 MSP430G2744

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RHA40
      3.      YFF49
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL12
    2. 6.2  BCL16
    3. 6.3  CPU19
    4. 6.4  CPU45
    5. 6.5  EEM20
    6. 6.6  FLASH24
    7. 6.7  FLASH27
    8. 6.8  FLASH36
    9. 6.9  PORT10
    10. 6.10 SYS15
    11. 6.11 TA12
    12. 6.12 TA16
    13. 6.13 TA21
    14. 6.14 TAB22
    15. 6.15 TB2
    16. 6.16 TB16
    17. 6.17 TB24
    18. 6.18 USCI20
    19. 6.19 USCI21
    20. 6.20 USCI22
    21. 6.21 USCI23
    22. 6.22 USCI24
    23. 6.23 USCI25
    24. 6.24 USCI26
    25. 6.25 USCI27
    26. 6.26 USCI30
    27. 6.27 USCI34
    28. 6.28 USCI35
    29. 6.29 USCI40
    30. 6.30 XOSC5
  7. 7Revision History

6.2 BCL16

BCL Module

Category

Functional

Function

SMCLK clock source selection from XT1/VLO to DCO

Description

When the MCLK and the SMCLK do not use the DCO, the DCO is off. The DCO does not start if the clock source for SMCLK is changed from XT1/VLO to DCO. As a result, the SMCLK remains high. Note: This is only true for SMCLK. The DCO starts if the clock source of MCLK is set to DCO.

Workaround

Set clock source of MCLK to DCO by either:

1)setting the selection bits SELMx of BCSCTL2 register to '00' or '01'.

OR

2)setting the OFIFG bit of IFG1 register. Note: This triggers the oscillator fault logic that automatically starts the DCO. Reset the OFIFG bit to further use the XT1/VLO.


For both options, if the XT1/VLO is still required to source MCLK, revert the clock source of MCLK back to XT1/VLO afterwards.