SLAZ758D November   2024  – December 2025 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  ADC_ERR_06
    2. 6.2  ADC_ERR_10
    3. 6.3  AES_ERR_01
    4. 6.4  CPU_ERR_02
    5. 6.5  CPU_ERR_03
    6. 6.6  FLASH_ERR_01
    7. 6.7  FLASH_ERR_03
    8. 6.8  FLASH_ERR_04
    9. 6.9  FLASH_ERR_05
    10. 6.10 FLASH_ERR_08
    11. 6.11 GPIO_ERR_03
    12. 6.12 GPIO_ERR_04
    13. 6.13 I2C_ERR_04
    14. 6.14 I2C_ERR_05
    15. 6.15 I2C_ERR_06
    16. 6.16 I2C_ERR_07
    17. 6.17 I2C_ERR_08
    18. 6.18 I2C_ERR_09
    19. 6.19 I2C_ERR_10
    20. 6.20 I2C_ERR_13
    21. 6.21 KEYSTORE_ERR_01
    22. 6.22 MATHACL_ERR_01
    23. 6.23 MATHACL_ERR_02
    24. 6.24 PMCU_ERR_09
    25. 6.25 PMCU_ERR_10
    26. 6.26 PMCU_ERR_11
    27. 6.27 RST_ERR_01
    28. 6.28 RTC_ERR_01
    29. 6.29 SPI_ERR_02
    30. 6.30 SPI_ERR_04
    31. 6.31 SPI_ERR_05
    32. 6.32 SPI_ERR_06
    33. 6.33 SPI_ERR_07
    34. 6.34 SRAM_ERR_03
    35. 6.35 SYSCTL_ERR_01
    36. 6.36 SYSCTL_ERR_02
    37. 6.37 SYSCTL_ERR_03
    38. 6.38 SYSCTL_ERR_04
    39. 6.39 SYSOSC_ERR_01
    40. 6.40 SYSOSC_ERR_02
    41. 6.41 SYSOSC_ERR_04
    42. 6.42 SYSPLL_ERR_01
    43. 6.43 TIMER_ERR_04
    44. 6.44 TIMER_ERR_06
    45. 6.45 TIMER_ERR_07
    46. 6.46 UART_ERR_01
    47. 6.47 UART_ERR_02
    48. 6.48 UART_ERR_04
    49. 6.49 UART_ERR_05
    50. 6.50 UART_ERR_06
    51. 6.51 UART_ERR_07
    52. 6.52 UART_ERR_08
    53. 6.53 UART_ERR_10
    54. 6.54 UART_ERR_11
  9. 7Trademarks
  10. 8Revision History

6.42 SYSPLL_ERR_01

SYSPLL Module

Category

Functional

Function

SYSPLL Frequency may not lock to correct frequency when enabled.

Description

When setting the SYSPLLEN bit to 1 in SYSCTL HSCLKEN register, the SYSPLL will run the phase locked loop search. The search can potentially fail where the frequency will not be set to the correct value, instead the resultant frequency will be drastically different than the configured frequency.

Workaround

Check the frequency output of the SYSPLL using the Frequency Clock Counter (FCC) anytime the SYSPLLEN bit is set to 1. Once the frequency is correct it will maintain the correct value until disabled and reenabled (SYSPLLEN set to 0 then 1), once reenabled the PLL will re-run the search and the SYSPLL output will need to be rechecked.

Workaround 1: Set FCC with SYSPLLCLK0 as the CLK input and LFCLK as the Trigger source. Run the FCC and check the value for the configured SYSPLL frequency with reference to the LFCLK; for example, with SYSPLL = 80MHz and LFCLK = 32kHz, the resultant FCC count should be 80,000,000/32,768= ~2441. The count will vary depending on the combined clock accuracies, so it is recommended to add a +-5% to allowed range. Estimated time for FCC is 30us.

FCC Settings: SYSCTL.GENCLKCFG.FCCTRIGCNT = 0, SYSCTL.GENCLKCFG.FCCTRIGSRC = 1, SYSCTL.GENCLKCFG.FCCSELCLK = 4;

If the FCC value is incorrect, disable and reenable the SYSPLL by setting SYSPLLEN to 0 then 1. Rerun the FCC check.

Workaround 2: Output SYSOSC/2 from the CLK_OUT pin and route the signal into FCC_IN. Use the SYSPLLCLK0 as the FCC CLK and the FCC_IN  for the trigger source. Run the FCC for 16 Clock cycles, and check the value for the configured SYSPLL frequency with reference to the SYSOSC; for example, with SYSPLL = 80MHz and SYSOSC/2 = 16MHz, the resultant FCC count should be 80,000,000/16,000,000 * 16  = ~80. The count will vary depending on the combined clock accuracies, so it is recommended to add a +-5% to allowed range. Estimated time for FCC is 1us.

FCC Settings: SYSCTL.GENCLKCFG.FCCTRIGCNT = 0x0F, SYSCTL.GENCLKCFG.FCCTRIGSRC = 0, SYSCTL.GENCLKCFG.FCCSELCLK = 4;

If the FCC value is incorrect, disable and reenable the SYSPLL by setting SYSPLLEN to 0 then 1. Rerun the FCC check.