SLDS273A September   2024  – March 2025 DRV81080-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active Mode
          5. 7.3.2.1.5 Limp Home Mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home Mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
      2. 8.1.2 Application Plots
    2. 8.2 Typical Application
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 Power Supply

The DRV81080-Q1 is supplied by four supply voltages:

  • VM (analog supply voltage used also for the logic)
  • VM1 (analog supply voltage used as drain for channels 0, 2, 4 and 6)
  • VM2 (analog supply voltage used as drain for channels 1, 3, 5 and 7)

  • VDD (digital supply voltage)

The VM supply is connected to a battery feed and used, in combination with VDD supply, for the driving circuitry of the power stages. In situations where VM voltage drops below VDD voltage (for example during cranking events down to 3V), an increased current consumption can be observed at VDD pin. VM and VDD supply voltages have an undervoltage detection circuit.

  • An undervoltage on both VM and VDD supply voltages prevents the activation of the power stages and any SPI communication (the SPI registers are reset)
  • An undervoltage on VDD supply prevents any SPI communication. SPI read/write registers are reset to default values.
  • An undervoltage on VM supply forces the device to drain all needed current for the logic from VDD supply. All channels are disabled, and are enabled again as soon as VM ≥ VM_OP.

The image below shows a basic concept drawing of the interaction between supply pins VM and VDD, the output stage drivers and SDO supply line.

DRV81080-Q1 Internal Power Supply Architecture Figure 7-3 Internal Power Supply Architecture

When 3V ≤ VM ≤ VDD - VMDIFF, the device operates in Cranking Operative Range (COR). In this condition, the current consumption from VDD pin increases while current consumption decreases from VM pin. Total current consumption remains within the specified limits.

Figure 7-4 shows the voltage levels at VM pin where the device goes in and out of COR. During the transition to and from COR, IVM and IVDD change between values defined for normal operation and for COR operation. The sum of both current remains within limits specified in Section 6.5.

DRV81080-Q1 Cranking Operative Range Figure 7-4 Cranking Operative Range

When VM_UVLO ≤ VM ≤ VM_OP, it may be not possible to switch ON a channel that was previously OFF. All channels that are already ON keep the state unless the channels are switched OFF via SPI or via IN pins. An overview of channel behavior according to different VM and VDD supply voltages is shown in Table 7-2, Table 7-3 and Table 7-4 (the tables are valid after a successful power-up).

Table 7-2 Channel Control as Function of VM and VDD
VDD ≤ VDD_UVLO VDD > VDD_UVLO
VM ≤ 3V Channels cannot be controlled Channels can be switched ON and OFF (SPI control)(RDS(ON) deviations possible)
3V < VM ≤ VM_OP Channels cannot be controlled by SPI Channels can be switched ON and OFF (SPI control)(RDS(ON) deviations possible)
VM > VM_OP Channels cannot be controlled by SPI Channels can be switched ON and OFF
Table 7-3 Limp Home Mode as Function of VM and VDD
VDD ≤ VDD_UVLO VDD > VDD_UVLO
VM ≤ 3V Not available Available (RDS(ON) deviations possible)
3V < VM ≤ VM_OP Available (RDS(ON) deviations possible) Available (RDS(ON) deviations possible)
VM > VM_OP Available Available
Table 7-4 SPI Registers and SPI Communication as Function of VM and VDD
VDD ≤ VDD_UVLO VDD > VDD_UVLO

SPI Registers

 Reset Available

SPI Communication

 Not available (fSCLK = 0MHz) Possible (fSCLK = 5MHz)