SLLA489A May   2020  – December 2025 ISO7021

 

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  2. 1Construction and Marking Report for ATEX / IECEx Certification
    1. 1.1 ISO7021 and ISO7021F Device Construction Information
    2. 1.2 Information About Pin Numbers and Pin Signal Names
    3. 1.3 Constructional Diagrams
    4. 1.4 Information About Creepage and Clearance Specification
    5. 1.5 Mechanical Data
    6. 1.6 Isolation Capacitor Technology
    7. 1.7 Assembly Information
    8. 1.8 ISO7021 and ISO7021F Device Marking Information
      1. 1.8.1 Location and Details of Marking on the IC
  3. 2Revision History

1.6 Isolation Capacitor Technology

The primary isolation barrier in the ISO7021 and ISO7021F consists of two high-voltage isolation capacitors in series. Each capacitor resides inside the plastic package, on the left and right side chips, respectively. Both capacitors are connected to each other through inter-die bond wires. The isolation capacitors are integrated inside each die using TI’s proprietary LBC8LViso.2 chip fabrication process technology. Each isolation capacitor has a minimum dielectric thickness of 8.5µm, which is made up of SiO2, SiN, and SiON. The dielectric in each capacitor consists of three inter-metal dielectric (IMD) layers as shown in Table 1-2.

Table 1-2 Inter-metal Dielectric (IMD) Layers
CAP 1 LAYER #COMPOSITIONTYPICAL THICKNESS (µm)
IMD2SiO22.4
IMD3SiO23.7
IMD4SiO2, SiN, SiON3.7

The typical dielectric thickness of each capacitor is 9.8µm. Therefore, with two capacitors in series, each ISO7021 and ISO7021F device has typical dielectric thickness of 19.6µm and minimum thickness of 17µm. The SOIC-8 package lead frame has a pad-to-pad spacing of >0.4mm.